Analog Devices ADRV9005 Reference Manual page 104

Reference Manual
MULTICHIP SYNCHRONIZATION
To select one of the modes, use this structure:
typedef enum adi_adrv9001_McsMode {
ADI_ADRV9001_MCSMODE_DISABLED = 0, /*!< Multi Chip Synchronization disabled */
ADI_ADRV9001_MCSMODE_ENABLED, /*!< Multi Chip Synchronization enabled */
ADI_ADRV9001_MCSMODE_ENABLED_WITH_RFPLL_PHASE /*!< Multi Chip Synchronization enabled with RFPLL phase
*/
} adi_adrv9001_McsMode_e;
Frequency Hopping
For frequency hopping, choose one option from the Enum to enable MCS to have the deterministic delay or to add additional phase
synchronization. For the first option, consider only the PLL settling time as there is no additional phase synchronization required. For the
second option, an additional time is consumed, and this depends on the reference clock speed and the LO frequencies used for frequency
hopping.
Figure 89 shows the phase synchronization timing when it is required. Note: The higher the LO frequency and reference clock speed, the lower
the time it requires for phase synchronization. Consider this additional timing when designing frequency hopping with phase synchronization.
Figure 90 shows the theoretical phase synchronization timing up to 6 GHz. The actual time varies but should be close to the theoretical limit.
For frequency hopping, if phase synchronization is not needed, select the MCS only mode. In this case, do not care about the phase
synchronization time as it is disabled. There is no additional timing consideration because all the MCS is done at the initial stage, not at the hop
stage.
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Figure 89. PLL Phase Synchronization Time vs. LO Frequency and Fref
Figure 90. Theoretical Phase Sync Time up to 6GHz
ADRV9001
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