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Analog Devices ADRV9001 User Manual

Analog Devices ADRV9001 User Manual

System development user guide for the rf agile transceiver family
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ADRV9001 System Development User Guide
UG-1828
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Preliminary Technical Data
System Development User Guide for the RF Agile Transceiver Family

ADRV9001 TRANSCEIVER OVERVIEW

The ADRV9001 is a highly integrated, RF agile transceiver family offering two independently controlled transmitters, two independently
controlled receivers, integrated synthesizers, and digital signal processing functions. This document is designed to encompass
description of all functions available in the ADRV9001 family of products. Note that some variants may be developed for specific design
targets that do not encompass all available functions, so refer to the data sheet for the specific device to determine which features are
included.
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
Rev. PrA | Page 1 of 253
WARNING AND LEGAL TERMS AND CONDITIONS.

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Summary of Contents for Analog Devices ADRV9001

  • Page 1: Adrv9001 Transceiver Overview

    This document is designed to encompass description of all functions available in the ADRV9001 family of products. Note that some variants may be developed for specific design targets that do not encompass all available functions, so refer to the data sheet for the specific device to determine which features are included.

  • Page 2: Table Of Contents

    RF Synthesizer ................79   Application .................. 14   Auxiliary Synthesizer ..............80   ADRV9001 in 1T1R FDD with DPD Type Application ..16   External LO ................. 80   ADRV9001 in TETRA Type Portable Radio Application ..18  ...
  • Page 3 Component Placement and Routing Priorities ....209 Digital Predistortion ..............162 RF and Data Port Transmission Line Layout ....... 215 Background ................162 Isolation Techniques Used on the ADRV9001 Evaluation ADRV9001 DPD Function ............. 162 Card .................... 222 ADRV9001 DPD Supported Waveforms ......163 Power Supply Recommendations ..........
  • Page 4 UG-1828 Preliminary Technical Data Tracking Calibrations .............. 246 Power Savings and Monitor Mode ........249 Digital Pre-Distortion .............. 247 Log File ..................250 TDD Enablement Delays ............247 Using of Matlab and Python........... 251 Auxiliary DAC/ADC ............... 247 Evaluation System Troubleshooting ........251 Radio state .................

  • Page 5: How To Use This Document

    Preliminary Technical Data UG-1828 HOW TO USE THIS DOCUMENT START GO TO ADRV9001 TRANSCEIVER OVERVIEW AND LEARN WHAT ADRV9001 IS? ADRV9001 EXAMPLE USE CASES PARAGRAPHS. GO TO ADRV9001 EVALUATION SYSTEM HAVE ADRV9001 PARAGRAPH FOR MORE INFORMATION EVALUATION SYSTEM? HOW TO USE IT.

  • Page 6: Adrv9002 Block Diagram

    UG-1828 Preliminary Technical Data ADRV9002 BLOCK DIAGRAM RX1A+ DIGITAL SIGNAL PROCESSING: RX1_DCLK_OUT± RX1A– - NARROW/WIDE BAND DECIMATION DATA - DC OFFSET CORRECTION (DC) 0° PORT - QUADRATURE ERROR CORRECTION (QEC) RX1_STROBE_OUT± CMOS-SSI - NUMERICALLY CONTROLLED OSCILLATOR (NCO) 90° - PROGRAMMABLE FIR FILTER (PFIR) RX1B+ LVDS-SSI - AUTOMATIC GAIN CONTROL (AGC)

  • Page 7: Product Highlights

    Preliminary Technical Data UG-1828 PRODUCT HIGHLIGHTS ADRV9002 ADRV9002 delivers a versatile combination of high performance and low power consumption required by battery powered radio equipment and can operate in both frequency division duplex (FDD) and time division duplex (TDD) modes. The ADRV9002 operates from 30 MHz to 6000 MHz covering the VHF, licensed and unlicensed cellular bands, and ISM bands.
  • Page 8 UG-1828 Preliminary Technical Data The LVDS electrical interface supports two modes of operation. The 32 total bits of I and Q data are serialized over one LVDS lane (32 bits composed of 16 bits of I and 16 bits of Q data) or two LVDS-SSI lanes (each dedicated to 16 bits of I or Q data), with two additional lanes total required for a DDR clock and a frame synchronization signal.
  • Page 9 Preliminary Technical Data UG-1828 The ADC in the receive chain possesses a high dynamic range. Assuming a mixer gain of 0 dB, the ADC’s noise and maximum input power referred to the RF input are -142 dBm/Hz and 8.6 dBm, respectively. These levels translate into a dynamic range in excess of 150 dB on a per Hertz basis.

  • Page 10: Adrv9001 Example Use Cases

    ADRV9001 EXAMPLE USE CASES Intention of this section is to provide reader with overall idea how ADRV9001 integrated transceiver can operate as RF Front End in different applications. Provided list is not exhaustive and there are other aplications where ADRV9001 can serve.
  • Page 11 Digital GPIOs can be used to perform real time monitoring of states of internal ADRV9001 blocks. Digital GPIOs DGPIOs operating as inputs can allow user to control Rx gain, Tx attenuation, AGC operation and other elements of ADRV9001 TRx. Depending on the ADRV9001 operation up to 4 GPIOs may be utilized by data port interface.

  • Page 12: Adrv9001 In Dual-Band 2Rt2R Fdd Type Small-Cell Application

    RF RECEPTION BAND B (DIVERSITY/MIMO) AND Tx INIT CALIBRATIONS RF TRANSMISSION BAND A AND BAND B (DIVERSITY/MIMO) RF TRANSMISSION BAND A AND BAND B (DIVERSITY/MIMO) Figure 4. ADRV9001 in Dual-Band 2T2R FDD Type Small-Cell Application Rev. PrA | Page 12 of 253...
  • Page 13 LO Generation In FDD type Small cell application, ADRV9001 can use its internal LO to generate RF LO1 for uplink (Rx1 and Rx2) and RF LO2 for downlink (Tx1 and Tx2). It is also possible to use external LO inputs in this mode of operation. External LO1 operating at 2x RF LO can be used for uplink and External LO2 operating at 2x RF LO can be used for downlink.

  • Page 14: Adrv9001 In Single-Band 2T2R Tdd Type Small-Cell Application

    ADRV9001 transceiver with minimum number of external components can be utilized to build complete RF-to-bits signal chain that can serve as RF front end in TDD type small cell type applications. ADRV9001 dual Rx and Tx signal chains enables user to implement MIMO or diversity in their system.
  • Page 15 LO Generation In TDD type Small Cell application, ADRV9001 can use its internal LO to generate RF LO1 for both uplink and downlink. It is also possible to use external LO inputs in this mode of operation. External LO1 operating at 2x RF LO can be used for both uplink and downlink.

  • Page 16: Adrv9001 In 1T1R Fdd With Dpd Type Application

    For systems that demand superior LO phase noise performance ADRV9001 allows user to apply eternal RF LO. ADRV9001 internal AGC can be utilized to autonomously monitor and set appropriate gain level for Rx signal chain.
  • Page 17 LO Generation In 1T1R FDD+DPD type applications, ADRV9001 can use its internal LO to generate RF LO1 for uplink and RF LO2 for downlink. For applications with stringent RF LO requirements, user can use external LO inputs. External LO1 operating at 2x RF LO can be used for uplink and separate external LO2 operating at 2x RF LO for downlink.

  • Page 18: Adrv9001 In Tetra Type Portable Radio Application

    For systems that demand superior LO phase noise performance ADRV9001 allows user to apply eternal RF LO. ADRV9001 internal AGC can be utilized to autonomously monitor and set appropriate gain level for Rx signal chain. For time critical TDD type applications control of the ADRV9001 TRx can be done by toggling control lines.
  • Page 19 The DPD functionality can be utilized in the 1T1R TDD mode. Maximum channel bandwidth that DPD can support is imited by ADRV9001 RF bandwidth divided by 3 or by 5. The DPD operation can be performed by ADRV9001 or Rx data can be sent to baseband processor via Rx data port during Tx operation.

  • Page 20: Adrv9001 In Dmr Type Portable Radio Application

    RF front end in DMR type applications. For systems that demand superior LO phase noise performance ADRV9001 allows user to apply eternal RF LO. ADRV9001 internal AGC can be utilized to autonomously monitor and set appropriate gain level for Rx signal chain.
  • Page 21 DGPIOs For DMR type applications ADRV9001 supports RF Monitor mode of operation. DGPIO pins are used to: sent wake up signal to baseband processor, allow baseband processor to move ADRV9001 into Monitor mode using hardware pins (instead API command).

  • Page 22: Adrv9001 In Fdd Type Repeater Application

    RF front end in repeater or frequency translator type applications. ADRV9001 internal AGC can be utilized to autonomously monitor and set appropriate gain level for Rx signal chains. For none time critical FDD type applications control of the ADRV9001 TRx can be done thru API commands that utilize SPI interface.
  • Page 23 Digital GPIOs can be used to perform real time monitoring of states of internal ADRV9001 blocks Digital GPIOs operating as inputs can allow user to control Rx gain, Tx attenuation, AGC operation and other elements of ADRV9001 TRx. Depending on the ADRV9001 operation up to 4 GPIOs may be utilized by data port interface.
  • Page 24 ADRV9001 internal AGC can be utilized to autonomously monitor and set appropriate gain level for Rx signal chains. For none time critical FDD type applications control of the ADRV9001 TRx can be done thru API commands that utilize SPI interface.
  • Page 25 RF Front End For LO generation, ADRV9001 utilize internal VCO that generates square wave type signal. A square wave LO would produce harmonics. For example: depending of RF matching used on the RF ports user 2nd LO harmonic can be as high as -50dBc and 3rd harmonic can be as high as -9 dBc.

  • Page 26: Adrv9001 In Tdd Type Repeater Application

    Rx signal chains. FPGA or baseband processor is responsible for appropriate time alignment of Rx and Tx time slots. Control of the ADRV9001 Rx and Tx signal chains can be done by toggling control lines.
  • Page 27 The DPD functionality can be utilized in the 2R2T TDD mode. Maximum channel bandwidth that DPD can support is limited by ADRV9001 RF bandwidth divided by 3 or by 5. The DPD operation can be performed by ADRV9001 or ORx data can be sent to baseband processor via Rx data port during Tx operation.

  • Page 28: Adrv9001 In Radar Type Application

    UG-1828 Preliminary Technical Data ADRV9001 IN RADAR TYPE APPLICATION Figure 12. ADRV9001 in Radar type application Rev. PrA | Page 28 of 253...
  • Page 29 ADRV9001 transceiver with minimum number of external components can be utilized to build complete RF-to-bits signal chain that can serve as RF front end building block in Radar type applications. ADRV9001 internal AGC can be utilized to autonomously monitor and set appropriate gain level for Rx signal chains.

  • Page 30: Software System Architecture Description

    HTML format. For security reasons, .chm files can only be opened from a local drive. If you attempt to open from a network drive, the file may look empty. Note that the ADRV9001 is baseline device for the product family; therefore, all API and evaluation systems use this product number to delineate the product.

  • Page 31: Folder Structure

    /c_src/devices The devices folder includes the main API code for the ADRV9001 transceiver as well as auxiliary devices APIs used for the demo of ADRV9001. The /adrv9001 folder contains the high level function prototypes, data types, macros, and source code used to build the final user software system.
  • Page 32 The /platforms folder provides the means for a developer to insert custom platform hardware driver code for system integration with the ADRV9001 API. A description regarding the HAL interface is contained later in this document. The adi_platform.c/.h files contain function pointers and the required prototypes necessary for the ADRV9001 API to work correctly. Modification of the function prototypes in adi_platform.c is forbidden.

  • Page 33: Software Integration

    ADI evaluation platform. The hardware abstraction layer (HAL) interface is a set of function pointers that the ADRV9001 API uses when it needs to access the target platform hardware. The ADI HAL is defined in adi_platform.h.

  • Page 34: Developing The Application

    HAL function as a void *devHalCfg. ADRV9001 API functions shall not read or write the devHalInfo but pass it as parameter to all HAL function calls. The Application developer must define devHalInfo per system HAL implementation requirements. The Application developer may implement any structure to pass any hardware configuration information that the hardware requires between application layer and platform layer.
  • Page 35 The developer may need to store other hardware information unique to a particular ADRV9001 device in this structure such as timer instances or log file information. Note for ADRV9001 API there is a requirement that only one thread may control and configure a specific device instance at any given time.

  • Page 36: System Initialization And Shutdown

    TES CONFIGURATION AND INITIALIZATION The TES provides a Config tab that contains all the setup options for the ADRV9001. Under the Config tab, the user could configure each channel of the device for a desired profile under the Device Configuration subtab, which sets high level parameters such as duplex mode, data port sample rates and RF channel bandwidth.

  • Page 37: Api Initialization Sequence

    API functions are discussed briefly in the following subsections. Refer to the doxygen document for details of each API function. Note for MIMO systems with multiple inputs and outputs channels, multiple ADRV9001 devices might be involved. To synchronize among all the devices, it requires a common device clock (DEV_CLOCK) and a multichip synchronization (MCS) signal so that all the internally generated analog and digital clocks are aligned among all the devices.
  • Page 38 UG-1828 Preliminary Technical Data and baseband processor data interface for all devices. For simplicity, in the following descriptions, MCS operations are omitted from the initialization steps. Refer to Clock Generation and Multichip Synchronization section in the user guide for more details. Analog Initialization Analog initialization API adi_adrv9001_InitAnalog() is the very first API call to configure the device after all dependent data structures have been initialized.

  • Page 39: Shutdown Sequence

    After completing all the operations, the user should call API adi_adrv9001_Shutdown() through TES to safely shutdown ADRV9001 device. It performs a hardware reset to reset the ADRV9001 device into a safe state for shutdown or re-initialization. Rev. PrA | Page 39 of 253...

  • Page 40: Serial Peripheral Interface (Spi)

    5pF load @ 75 MHz 0x01 0x01 100pF load @ 20 MHz Any value that is not listed in the table is invalid. For more details please refer to ADRV9001_API doxygen file provided in ADRV9001 SDK package. Rev. PrA | Page 40 of 253...

  • Page 41: Spi Bus Signals

    Preliminary Technical Data UG-1828 SPI BUS SIGNALS The SPI bus consists of the following signals: SCLK SCLK is the serial interface reference clock driven by the baseband processor (uses the SPI_CLK pin). It is only active while CSB is low. The minimum SCLK frequency is 1 KHz.
  • Page 42 UG-1828 Preliminary Technical Data In LSB mode, the LSB of the address is the first bit transmitted from the baseband processor, followed by the next 14 bits in order from next LSB to MSB. The next bit signifies if the operation is read (set) or write (clear). If the operation is a write, the baseband processor transmits the next 8 bits LSB to MSB.

  • Page 43: Timing Diagrams

    Preliminary Technical Data UG-1828 • Use the next 32 clock cycles to send the data to be written to the registers, MSB to LSB for each 8-bit word • Make sure the CSB line is driven high after the last bit has been sent to 0x027 to end the data transfer TIMING DIAGRAMS The diagrams in Figure 21 and Figure 22 illustrate the SPI bus waveforms for a single-register write operation and a single-register read operation, respectively.
  • Page 44 UG-1828 Preliminary Technical Data SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/W A14 A13 A12 A11 A10 A9 DON’T CARE Figure 22. 3-Wire SPI Timing with Parameter Labels, SPI Read Rev. PrA | Page 44 of 253...

  • Page 45: Data Interface

    One lane data mode, I/Q data or other format data are serialized onto one single lane. • Four lanes data mode, which is valid only when ADRV9001 transmit or receive I/Q samples and I/Q samples are 16 bits wide. In •...
  • Page 46 In LVDS mode, an external 100 Ω differential termination resistor is required for each LVDS pair, and the termination resistors should be located as close as possible to the LVDS receiver. ADRV9001 LVDS in circuit has optional internal 100 Ω termination resistor which can be enabled for LSSI, but ADRV9001 LVDS output circuit does not have internal termination resistors, users should develop appropriate LVDS termination resistors in LVDS receiver.

  • Page 47: Cmos Synchronous Serial Interface (Cmos-Ssi)

    Preliminary Technical Data UG-1828 Table 15. CSSI Electrical Specification Symbol Parameter Units VDIGIO_1P8 Interface power supply voltage 1.71 1.89 Input voltage high VDIGIO_1P8 × 0.65 VDIGIO_1P8 + 0.18 Input voltage low VDIGIO_1P8 × 0.35 Output voltage high VDIGIO_1P8 − 0.45 VDIGIO_1P8 Output voltage low 0.45...
  • Page 48 (refer to the Transmitter Signal Chain and Rx Demodulator sections), the data transfer between ADRV9001 and baseband processor would be 2 bits or 16 bits I only data ( denoted as symbol to differentiate with I/Q complex samples).
  • Page 49 Preliminary Technical Data UG-1828 Figure 26 illustrates the receive CSSI interface (Rx) for 2-bit data symbols. RX_DCLK_OUT RX_STROBE_OUT RX_DATA_OUT S0_D1 S0_D0 S1_D1 S1_D0 S2_D1 S2_D0 S3_D1 Figure 26. Receive CSSI Timing for 2-Bit Symbols (MSB First) Figure 27 illustrates the transmit CSSI interface (Tx) for 2-bit data symbols. TX_DCLK_OUT TX_DCLK_IN TX_STROBE_IN...
  • Page 50 Receive CSSI Interface with 2×, 4×, and 8× Data Clock Rates ADRV9001 receive CSSI supports the 2 times, 4 times, or 8 times of the data clock rate for some applications. Figure 32, Figure 33, and Figure 34 illustrate the receive CSSI interface (Rx1 and Rx2) for 16-bit I/Q data sample with 2×, 4×, and 8×...
  • Page 51 Preliminary Technical Data UG-1828 16 CYCLES (I SAMPLE) 16 CYCLES (Q SAMPLE) 224 CYCLES (NO SAMPLE) RX_DCLK_OUT RX_STROBE_OUT RX_STROBE_OUT RX_DATA_OUT I0_D15 I0_D14 I0_D0 Q0_D15 Q0_D14 Q0_D0 I1_D15 I0_D14 Figure 34. Receive CSSI timing with 8× Data Clock Rate for 16-Bit I/Q Data Sample (MSB First), 224 Cycles Figure 35, Figure 36, and Figure 37 illustrate the Receive CSSI interface (Rx1 and Rx2) in frequency deviation mode with 16-bit data symbol with 2×, 4×, and 8×...
  • Page 52 UG-1828 Preliminary Technical Data Figure 39 illustrates the receive CSSI interface (Rx1 and Rx2) for a four-lane format with MSB first configuration. RX_DCLK_OUT RX_STROBE_OUT RX_STROBE_OUT I0_D7 I0_D6 I0_D5 I0_D4 I0_D3 I0_D2 I0_D1 I0_D0 I1_D7 RX_IDATA0_OUT I0_D15 I0_D14 I0_D13 I0_D12 I0_D11 I0_D10 I0_D9 I0_D8...
  • Page 53 (positive and negative) samples the corresponding strobe/data sample based on the interface setup/hold timing. When the baseband processor drives out the transmit SSI clock, strobe and data to ADRV9001, the output DDR clock can be in-phase with the strobe/data or delayed quarter cycle of the clock period, it’s up to the user, but the relation between transmit DDR clock and strobe/data must meet the ADRV9001 setup and hold timing specification.

  • Page 54: Lvds Synchronous Serial Interface (Lvds-Ssi)

    UG-1828 Preliminary Technical Data TX_DCLK_OUT TX_DCLK_IN TX_DCLK_IN TX_STROBE_IN TX_STROBE_IN I0_D7 I0_D6 I0_D5 I0_D4 I0_D3 I0_D2 I0_D1 I0_D0 I1_D7 TX_IDATA0_IN I0_D15 I0_D14 I0_D13 I0_D12 I0_D11 I0_D10 I0_D9 I0_D8 I1_D15 TX_IDATA1_IN Q0_D7 Q0_D6 Q0_D5 Q0_D4 Q0_D3 Q0_D2 Q0_D1 Q0_D0 Q1_D7 TX_QDATA2_IN Q0_D15 Q0_D14 Q0_D13 Q0_D12...
  • Page 55 Preliminary Technical Data UG-1828 RX_DCLK_OUT+ RX_DCLK_OUT+ RX_STROBE_OUT+ RX_STROBE_OUT+ I0_D11 I0_D6 I0_D5 I0_D0 I1_D11 I1_D10 RX_IDATA_OUT+/– Q0_D11 Q0_D6 Q0_D5 Q0_D0 Q1_D11 Q1_D10 RX_QDATA_OUT+/– Figure 45. Receive LSSI Timing for 12-Bit I/Q Data Sample over Two Lanes (MSB First) The RX_STROBE signal is aligned with the first bit of the serialized data (I and Q), and can be configured to be high: For a half clock cycle at start of I and Q sample transmit.
  • Page 56 UG-1828 Preliminary Technical Data An additional port might be used as a reference clock for the baseband processor to generate above Transmit LSSI clock, Strobe and Data signal, the user could use RX1_DCLK_OUT or RX2_DCLK_OUT as a reference clock if these clock frequencies are equal to the TX clock frequency.

  • Page 57: Ssi Timing Parameters

    Preliminary Technical Data UG-1828 Transmit LSSI Interface with One Lane for I and Q In this mode, only one lane is used to transfer I and Q data samples. The I/Q data bits can be deserialized with configurable I or Q first and MSB or LSB first.

  • Page 58: Cssi/Lssi Testability And Debug

    TX_STROBE_IN signal validity according the SSI work modes and reports the error flag if finds the strobe misalignment. ADRV9001 transmit SSI data output can be loopback to receive SSI data input when transmit and receive SSI runs at same clock rate, users can utilize themselves pattern generator and checker to verify if the whole system SSI works well.

  • Page 59: Api Programming

    Preliminary Technical Data UG-1828 API PROGRAMMING The ADRV9001 SSI configuration is performed in chip initialization stage and based on the following data structure. typedef struct adi_adrv9001_SsiConfig adi_adrv9001_SsiType_e ssiType; adi_adrv9001_SsiDataFormat_e ssiDataFormatSel; adi_adrv9001_SsiNumLane_e numLaneSel; adi_adrv9001_SsiStrobeType_e strobeType; uint8_t lsbFirst; uint8_t qFirst; bool refClockGpioEn;...

  • Page 60: Microprocessor And System Control

    For this reason, it is necessary to utilize a stream image for each configuration of the device. In this way, when the user saves configuration files (.c) using the ADRV9001 TES, a stream image is also saved automatically.

  • Page 61: System Control

    Tx2 datapath For ADRV9001 to receive and react to control signals it needs to be moved to the primed state. The primed state indicates that the system is ready for operation when the transmit and receive channels are enabled by the user. After the channel is primed, in order to start transmit or reception activities, it needs to be further transitioned from the primed state to the RF_ENABLED state.
  • Page 62 ADRV9001 further controls the transmitter interface, transmitter internal analog components, as well as the antenna switch (if it is controlled by ADRV9001 instead of user) to make sure that the transmit burst is on air at deterministic time as desired by user.
  • Page 63 Figure 54. This could achieve better power saving. For example, if the user measures the propagation delay as 2.5 ms, whereas the enableSetupDelay provided by ADRV9001 is 8 μs, analog front end could be off to avoid burning power for the first 2.492 ms of the propagation time.
  • Page 64 When the frame ends, enableFallToOffDelay could be set in a similar way as discussed in Use Case 1. Note ADRV9001 currently is not controlling the antenna switch, therefore it is the user’s responsibility to switch the antenna on and off at the accurate time.
  • Page 65 RX_ENABLE signal and a set of receive timing parameters configured by user, ADRV9001 further controls receive analog components, receive interface, and the external LNA (if it is controlled by ADRV9001 instead of user) to make sure that the received Rx burst is sent to BBIC at the deterministic time as desired by user.
  • Page 66 When the frame ends, user may wish to continue receiving for a while, however, ADRV9001 may wish to stop all the tracking algorithms to avoid any performance degradation. This can be achieved by bringing the RX_ENABLE signal low as soon as the frame ends but...
  • Page 67 (Note enableFallToOffDelay is forced to 0 currently by ADRV9001.). This time should be no larger than the guard time before the next frame. The longer this value, the later the next Rx_enable rising edge can occur.
  • Page 68 Timing Parameters with Power Savings Modes ADRV9001 offers several channel power savings modes (Power Saving Mode 0, Power Saving Mode 1, and Power Saving Mode 2) that trade off better power savings with longer transition time to turn on and turn off a transmit or receive channel. Please refer to the Power Saving and Monitor Mode section in this User Guide for more details about power saving modes.
  • Page 69 Timing Parameter Selection section for more details on hardware and software restrictions. Similarly, the same is true for Power Savings Mode 1, the ADRV9001 prevents the system from entering Power Savings Mode 1, unless enableRiseToAnalogOnDelay is set greater than t .
  • Page 70 For all channels the enableRiseToOnDelay must be greater than or equal to the enableRiseToAnalogOnDelay, provided the • enableRiseToOnDelay parameter is being used, that is, ADRV9001 is controlling antenna switch and/or LNA power. For transmitter channels, the enableHoldDelay must be less than or equal to the enableFallToOffDelay.
  • Page 71 } adi_adrv9001_ChannelEnablementDelays_t Note guardDelay is reserved for future use and forced to 0 by ADRV9001 for both transmitter and receiver channels. In addition to that, for the transmitter channel, holdDelay is also reserved for future use and forced to 0. For the receiver channel, fallToOffDelay is also reserved for future use and forced to 0.
  • Page 72 TxEnaFall2Off interface needs to be transmitted. Default Timing Parameters for Receiver Channels Figure 67 shows the ADRV9001 receiver required timing parameters and their minimum, maximum, and default values as well as some recommendations are summarized in Table 25. PIN: RX_ENABLE...
  • Page 73 As shown in Figure 68, only relevant channels are enabled for timing parameters configuration. User should enter all the values in ns. The propagation delay is a helper parameter, which is not needed by ADRV9001. It helps to set other timing parameters ADRV9001 requires.
  • Page 74 UG-1828 Preliminary Technical Data As aforementioned, API Command adi_adrv9001_Radio_ChannelEnablementDelays_Configure( ) can also be used to set the timing parameters. As a summary, all the APIs provided for timing parameters are listed in Table 26. Refer to the API doxygen document for more details.

  • Page 75: Clock Generation And Multichip Synchronization

    CLOCK GENERATION In ADRV9001 all clocks for the converters and main digital are generated by CLKGEN. CLKGEN receives from two clocks, a high performance (HP) clock PLL and a low power (LP) PLL. The high performance clock PLL has a programmable frequency range of 7.2 GHz to 8.8 GHz.

  • Page 76: Multichip Synchronization

    UG-1828 Preliminary Technical Data Table 28. Supported Data Lane Rate By LP CLKPLL Standard Serialization Factor Per Data Lane Data Lane Rate DMR/P25 Direct Modulation 9.60E +03 P25 Direct Modulation 1.20E +04 FM Direct Modulation 1.28E +05 DMR I/Q 7.68E + 05 1.92E + 05 3.84E + 05 FM Direct Modulation...

  • Page 77: Adrv9001 Communication With Bbic

    Figure 72. Illustration of MCS Pulse Sequence for MCS Synchronization ADRV9001 COMMUNICATION WITH BBIC ADRV9001 sleeps during MCS. BBIC is responsible to inform ARM before MCS operation and wake it afterwards. The ARM must wait for MCS signals in the following situations: During system initialization: the ARM is not yet enabled and no action is required from the firmware.
  • Page 78 UG-1828 Preliminary Technical Data Device Profile The device profile shall contain a uint8_t parameter called sysConfig.externalMcsSupported. Zero means only internal MCS is possible, non-zero means internal and external MCS are both available for the ARM to request. Request MCS from BBIC to ARM This signal is raised by the BBIC when it needs to do an unscheduled MCS.

  • Page 79: Synthesizer Configuration And Lo Operation

    SYNTHESIZER CONFIGURATION AND LO OPERATION The ADRV9001 family devices employ four phase-locked loop (PLL) synthesizers: clock, RF (×2), and auxiliary. Each PLL is based on a fractional-N architecture and consists of a common block made up of a reference clock divider, phase frequency detector, charge pump, loop filter, feedback divider, and digital control block, and either a 1 or 4 core voltage-controlled oscillator (VCO).

  • Page 80: Auxiliary Synthesizer

    UG-1828 Preliminary Technical Data RFLO1 MUX RFLO2 MUX TX1 MUX TX2 MUX RX1 MUX RX2 MUX Figure 75. LO Switching Network RFLO1 MUX RFLO2 MUX TX1 MUX TX2 MUX RX1 MUX RX2 MUX RX1/ORX1 RX2/ORX2 Figure 76. LO Switching Network (Receiver Channels Configured as Observation Receivers for Transmitter Channels) Note depending on the application, user has the ability to select best phase noise or best power saving options for better optimization.
  • Page 81 RF PLL Loop Filter Recommendations For optimal phase noise and EVM performance, a lookup table of RF PLL loop filter bandwidth settings is implemented in ADRV9001 firmware. ADRV9001 automatically selects best RF PLL loop filter configuration based on LO frequency. Alternatively, user can program its own RF PLL loop filter bandwidth following instruction outlined in Loop Filter Configuration paragraph.

  • Page 82: Api Operation

    API OPERATION Data Structure and Enums Table 29. Data Structures Related to LO Operation Data Structure Description adi_adrv9001_Device_t Data structure to hold ADRV9001 device instance settings. adi_adrv9001_Carrier_t Carrier structure for carrier configuration adi_common_Port_e Enumeration of port types. adi_common_ChannelNumber_e Enumeration of channel numbers.
  • Page 83 Preliminary Technical Data UG-1828 API Commands More detailed information including parameters, return values is provided in the doxygen document supplied with SDK package. Table 30. API Commands Related with LO Configuration Settings API Function Description adi_adrv9001_Channel_EnableRf() Enable or disable RF channel adi_adrv9001_Radio_PllStatus_Get() Checks if the PLLs are locked.

  • Page 84: Frequency Hopping

    Frequency hopping allows the user to quickly switch radio signals among different frequency channels. For ADRV9001, this is achieved by retuning the PLL before switching to the frequency channel. There are two local oscillators (LO) inside ADRV9001, therefore we can “ping-pong”...

  • Page 85: Framework

    DMA and stream processor are used internally and do not require user interaction. We mention these only for a more complete description of how different components work together for ADRV9001. From the user point of view, everything should work seamlessly.

  • Page 86: Modes Of Operation

    UG-1828 Preliminary Technical Data Automatic mode simply auto-increments in the frequency table. Table 32. Frequency and Gain Index Selection Modes Selection mode Notes Uses DGPIO pins for the user to provide a frequency and gain index. The number of frequencies or gain levels which can be indexed are restricted to the number of available DGPIOs. 6 DGPIOs are required to index a maximum of 64 operating frequencies.

  • Page 87: Configuration And User Information

    Preliminary Technical Data UG-1828 CONFIGURATION AND USER INFORMATION We ask the user to provide the following information to ADRV9001 for frequency hopping. Mode of Operation • Channel Mask for Hop 1 • Channel Select Mode • Frequency Select Mode •...
  • Page 88 UG-1828 Preliminary Technical Data BBIC LOADS DEVICE PROFILE FH DATA ARM IMAGE ... FH CONFIG INIT RADIO ID ITEMS FH MODE CHANNEL SELECT MODE RUN INIT CAL. FREQUENCY SELECT MODE ALGORITHMS STORE RESULTS. FH INIT CAL INFORMATION INIT CAL FREQ TABLE ID ITEMS ID FREQUENCY NUM INIT CAL FREQUECIES...

  • Page 89: Hop Time Example

    Preliminary Technical Data UG-1828 HOP TIME EXAMPLE BBIC Rx SETUP BBIC Tx SETUP BBIC FREQUENCY BBIC SELECT (MSG) RETUNE PLL PLL READY FRAME NO CHANNEL – – FREQUENCY – – – – Figure 84. Frequency Hopping (Fast Frequency Hopping Mode) Timing Diagram This example shows a frequency diagram for a 2-LO case for the Fast frequency hopping mode.

  • Page 90: Transmitter Signal Chain

    As mentioned earlier, the ADRV9001 supports many NB and WB standards. Depending on the selected standard and the specific symbol rate chosen via the API profile, the interface clock rate can vary significantly. For the currently supported use cases the interface rate can range from 9.6 kHz to 983.04 MHz.

  • Page 91: Digital Front End

    Transmit Gain Table The Tx attenuation block controls the Tx output power. A Tx gain table with 960 entries is loaded into the ADRV9001’s memory during initialization. (Currently only the first 840 entries are used and the remaining 120 entries are reserved for future use.) Each entry equals a 0.05dB gain step.
  • Page 92 UG-1828 Preliminary Technical Data maximum analog attenuation is 36 dB and the maximum digital attenuation is 6 dB. Note in direct FM/FSK mode, the maximum Tx attenuation is 12 dB with 0.5 dB step size. Table 37 shows the first 5 rows of the Tx gain table. Table 37.

  • Page 93: Bypass Mode

    Preliminary Technical Data UG-1828 Three Tx attenuation modes are provided as defined by the enum “adi_adrv9001_TxAttenuationControlMode_e”: typedef enum adi_adrv9001_TxAttenuationControlMode ADI_ADRV9001_TX_ATTENUATION_CONTROL_MODE_BYPASS = 0, ADI_ADRV9001_TX_ATTENUATION_CONTROL_MODE_SPI = 1, ADI_ADRV9001_TX_ATTENUATION_CONTROL_MODE_PIN = 3, } adi_adrv9001_TxAttenuationControlMode_e BYPASS MODE Bypass mode is selected when the Tx attenuation mode is set as “ADI_ADRV9001_TX_ATTENUATION_CONTROL_MODE_BYPASS”.

  • Page 94: Gpio Mode

    UG-1828 Preliminary Technical Data Tx OUTPUT POWER FULL-SCALE OUTPUT POWER DESIRED Tx ATTENUATION CONST_STEP_MODE_STEP_SIZE CONST_STEP_MODE_WAIT_DURATION TX_ATTENUATION<9:0> Figure 89. Constant Step Mode GPIO MODE Another method to control the Tx attenuation block is through GPIO mode. In this mode, two GPIO pins are used to increment or decrement the current attenuation value.
  • Page 95 Preliminary Technical Data UG-1828 Tx OUTPUT POWER PA_PROTECTION_AVG_DUR PEAK THRESHOLD AVERAGE THRESHOLD PA_PROTECTION_ERROR_FLAG PA_PROTECTION_RAMP_STEP_DURATION PA_PROTECTION_RAMP_MAX_ATTENUATION PA_PROTECTION_RAMP_STEP_SIZE TX_ATTENUATION Figure 91. Power Amplifier Monitor Slew Rate Limiter (SRL) The slew rate limiter is the other method for power amplifier protection. It essentially limits the rate of change of a waveform by continuously monitoring the difference between the input and output of the block and limiting the amount the output that can change during one cycle.

  • Page 96: Iq Fm/Fsk

    Preliminary Technical Data DPD is an optional feature available in the ADRV9001 device to enable users to achieve higher power amplifier efficiency while still meet Error Vector Magnitude (EVM) and adjacent channel leakage ratio (ACLR) requirements in their Tx signal chain for compliance with the standards requirements.

  • Page 97: Analog Front End (Afe)

    TRANSMIT DATA CHAIN API PROGRAMMING A set of Tx data chain APIs are provided for user interaction with the ADRV9001 device transmit datapath. Some of them have been discussed in the previous sections. The following table summarizes the list of API functions currently available with a brief description for each one.
  • Page 98 UG-1828 Preliminary Technical Data Rx Gain API Function Name Description adi_adrv9001_Tx_DacFullScaleBoost_Get Gets the DAC full scale current boost adi_adrv9001_Tx_AttenuationTable_Write Writes the attenuation table for the specified Tx channels adi_adrv9001_Tx_AttenuationTable_Read Reads the attenuation table for the specified Tx channels adi_adrv9001_Tx_NcoFrequency_Set Sets the Tx NCO test tone frequency for the specified Tx channel adi_adrv9001_Tx_NcoFrequency_Get Gets the Tx NCO test tone frequency for the specified Tx channel adi_adrv9001_Tx_PaProtection_Configure...

  • Page 99: Receiver/Observation Receiver Signal Chain

    Figure 94. Top Level Structure of ADRV9001 Dual Receiver Figure 94 describes the top-level structure of the ADRV9001 receivers. As shown in Figure 94, each receive path Rx1 or Rx2 contains 2 major subsystems, the Analog Front End (AFE) and the Digital Front End (DFE). The AFE subsystem contains 4 major components, which are programmable front end attenuator, matched I and Q mixer, low pass filter (LPF) and analog-to-digital converter (ADC).
  • Page 100 Figure 95. ADRV9001 Rx/ORx/Loopback Diagram The 3 loopback paths could also be used internally by ADRV9001 for two major purposes: Tx init calibrations and Tx tracking calibrations including the integrated digital pre-distortion (DPD) operation. Tx init calibrations is to configure the device properly based on system configurations during the initialization time.

  • Page 101: Receive Data Chain

    RECEIVE DATA CHAIN The ADRV9001 supports both NB and WB applications in a common design. Figure 96 describes the block diagram of the entire Rx data chain, which is composed of AFE and DFE. As mentioned earlier, the AFE includes a front end attenuator which controls the received RF signal level, mixer for RF to baseband (or IF) down-conversion, low pass filter and a pair of HP and LP ADCs.

  • Page 102: Analog Front-End Components

    The attenuator has 256 gain settings providing an Rx attenuation range from 0 to 20*log(1/256) = -48dB. Typically, only a subset of this range will be used. In ADRV9001, the range of the attenuation is from 0 to -36dB with a 0.5dB resolution. The gain of the attenuator is calculated by the following equation: The fe_gain_cw[7:0] is a 8 bit control word defined in the Rx gain table.

  • Page 103: Lpf

    As mentioned earlier, the ADRV9001 provides a pair of HP ADCs and a pair of LP ADCs to achieve a flexible trade-off between power consumption and linearity performance. The HP ADC is based on Continuous Time Delta Sigma (CTDS) architecture and is 5-bits wide.

  • Page 104: Dc Offset

    In ADRV9001, a two-step approach is taken to estimate and correct the dc offset. The first step comprises of an dc estimation step in digital domain and a correction procedure in the analog domain. The second step is an all-digital dc offset estimation and correction technique that estimates and corrects for any residual dc offset after the first step.

  • Page 105: Ddc

    Preliminary Technical Data UG-1828 Since ADRV9001 supports both NB and WB modes, NBQEC and WBQEC algorithms are developed accordingly to handle quadrature error in these 2 modes effectively. NBQEC employs a time-domain adaptive algorithm to estimate both gain and phase mismatch. Then, the estimations are applied to correct the distorted input signal in real-time before passing to DDC.

  • Page 106: Receive Data Chain Api Programming

    RECEIVE DATA CHAIN API PROGRAMMING A set of Rx data chain APIs are provided for user interaction with the ADRV9001 device receive datapath. Some of them have been briefly discussed in the previous sections. This set of APIs could be classified into 3 categories: Rx Gain APIs, Interface Gain APIs and Miscellaneous APIs as shown in Table 39, Table 40, and Table 41 respectively.

  • Page 107: Transmitter/Receiver/Observation Receiver Signal Chain Calibrations

    As discussed in Rx Signal Chain Section of this User Guide, ADRV9001 includes 2 Tx and 2 Rx. for each Rx, besides acting as a primary data channel for receiving RF signals, it could also serve as an observation channel, which receives Tx signals through loopback paths.
  • Page 108 Preliminary Technical Data Initial Calibrations API Programming The ADRV9001 ARM in the device is tasked with scheduling/performing initial calibrations to optimize the performance of the device prior to device operation. Initial calibrations is performed using the top-level API function adi_adrv9001_cals_InitCals_Run( ).
  • Page 109 Note non-channel related initial calibrations run implicitly, which are fully controlled by the ADRV9001 ARM. Table 42 describes the mask bit assignment for initial calibrations in adi_adrv9001_InitCalibrations_e. It also explains the functionality of each initial calibration.
  • Page 110 The ADRV9001 ARM proceeds through the calibrations in the required sequential order. The system initial calibrations are performed first followed by Rx initial calibrations and then Tx initial calibrations. The Rx initial calibration order and the Tx initial calibration order are shown in Table 43 and Table 44, respectively.
  • Page 111 In all the diagrams, grayed-out lines and blocks are not active in the calibration. Blue blocks are the related calibrations. It should be noted that as the ADRV9001 ARM performs each of the calibrations, it is tasked with configuring the ADRV9001 device as per the diagrams below, with respect to enabling/disabling paths, etc.
  • Page 112 QEC and LO_LEAKAGE correction values are applied to the transmitter channel by the ADRV9001 ARM. TX_DCC estimates the duty cycle error in the digital domain but applies the correction in the analog domain. Rev. PrA | Page 112 of 253...
  • Page 113 Receiver/Observation Receiver Signal Chain section, using ELB1 for initial calibrations provides the advantage of observing common mode voltage. When ELB1 is used, it has the same external system requirements as using ILB. Figure 100 shows the high level block diagram of initial Tx calibrations using internal signal generation and ELB1. ADRV9001 LNA SWITCH OFF 0°...
  • Page 114 In all the diagrams, grayed-out lines and blocks are not active in the calibration. Blue blocks are related calibrations. It should be noted that the ADRV9001 ARM performs each of the calibrations. It is tasked with configuring the ADRV9001 device as per the diagrams below, with respect to enabling/disabling paths, etc.
  • Page 115 Preliminary Technical Data UG-1828 Table 45. Initial Calibration Comparison Summary Initial Calibrations Run After LO Run after LO Change <100 Change MHz and Run >100 MHz or Signal Used User when Not ÷2 Run After ÷2 by Calibration External Override Run at Boundary Boundary...

  • Page 116: Tracking Calibrations

    All the tracking calibrations are fully controlled by the ADRV9001ARM therefore no user interaction is required. Tracking Calibrations API Programming The ADRV9001 ARM in the device is tasked with scheduling/performing tracking calibrations to optimize the performance of the device during its operation. Tracking calibrations are performed using the top-level API function adi_adrv9001_cals_Tracking_Set( ).
  • Page 117 Preliminary Technical Data UG-1828 In this structure, chanTrackingCalMask[] is an array containing calibration bit mask for channel related tracking calibrations (chanTrackingCalMask[0] is the mask for Rx1/Tx1 channels and chanTrackingCalMask[1] is the mask for Rx2/Tx2 channels ). The following enumerator type defines all the initial calibrations: typedef enum adi_adrv9001_TrackingCalibrations ADI_ADRV9001_TRACKING_CAL_TX_QEC = 0x00000001,...
  • Page 118 UG-1828 Preliminary Technical Data Bits Corresponding Enum Calibration Description ADI_ADRV9001_TRACKING_CAL_TX_PAC Tx PAC This is used to perform power amplifier correction. Tracking Currently this tracking calibration in not available. Calibration Tx DPD This is used to pre-distort the transmit signal in real-time ADI_ADRV9001_TRACKING_CAL_TX_DPD Tracking to compensate for the power amplifier nonlinearity for...
  • Page 119 Preliminary Technical Data UG-1828 For tracking calibrations, the TES provides the option to enable or disable those calibrations as shown in Figure 104. Note in the current release, the configurable Tx tracking calibrations are digital pre-distortion (TX_DPD), LO Leakage (TX_LO_LEAKAGE) and QEC (TX_QEC).

  • Page 120: Rx Gain Control

    RX GAIN CONTROL The ADRV9001 receivers (Rx1/Rx2) feature automatic and manual gain control modes for flexible gain control in a wide array of applications. It controls the gain at various stages of the Rx datapath to avoid overloading during the onset of a strong interferer. In addition, it could ensure that the Rx digital output data is representative of the RMS power of the Rx input signal so that any internal front-end gain changes to avoid overloading are transparent to the baseband processor.

  • Page 121: Receiver Datapath

    Figure 105 shows the simplified Rx datapath and gain control blocks. The receivers have front end attenuators prior to the mixer stage that are used to attenuate the signal in the analog domain to ensure the signal does not overload the receiver chain. Note ADRV9001 provides about 20dB gain so the front end gain attenuator further attenuates signal from that level.
  • Page 122 UG-1828 Preliminary Technical Data EXTERNAL FRONT END GAIN ATTENUATOR WB/NB DECIMATION HB FILTERING (DECIMATION GAIN GAIN (DECIMATION STAGE 2) STAGE 1) INTERFACE DIGITAL GAIN GAIN CONTROL (SLICER) ANALOG PEAK HB PEAK POWER RSSI DETECTOR DETECTOR DETECTOR GAIN CONTROL BLOCK (AGC, MGC) DGPIO(S) Figure 105.

  • Page 123: Gain Control Modes

    Preliminary Technical Data UG-1828 EXTERNAL ATTENUATOR AGPIO[0] AGPIO[1] Figure 106. AGPIO Control of an External Gain Element to Rx1 The 2 fields which are used in the gain table are the Front-end Attenuator and the Digital Gain/Attenuator. The Front-end Attenuator is an 8-bit control word.
  • Page 124 UG-1828 Preliminary Technical Data The APD and HB detector both have a high threshold and a low threshold, apdHighTresh, apdLowThresh, hbHighTresh and hbUnderRangeHighThresh, respectively. These levels are user programmable, as well as the number of times a threshold needs to be exceeded for an over range condition to be flagged.
  • Page 125 Preliminary Technical Data UG-1828 INTERFERER PRESENT GAIN DECREMENT (apdGainStepAttack/ hbGainStepAttack) GAIN DECREMENT (apdGainStepAttack/ apdHighThresh/ hbGainStepAttack) hbHighTresh SIGNAL LEVEL GAIN INCREMENT (apdGainStepRecovery/ hbGainStepHighRecovery) apdLowThresh/ hbUnderRangeHighTresh GAIN INCREMENT (apdGainStepRecovery/ GAIN UPDATE hbGainStepHighRecovery) PERIOD INTERFERER REMOVED Figure 107. APD/HB Thresholds and Gain Changes Associated with Underrange and Overrange Conditions It is possible to enable a fast attack mode whereby the AGC is instructed to reduce gain immediately when an over range condition occurs, instead of waiting until the next expiry of the gain update counter using changeGainIfThreshHigh.
  • Page 126 UG-1828 Preliminary Technical Data incremented by hbGainStepHighRecovery following the expiry of agcUnderRangeHighInterval, which is a multiple of agcUnderRangeMidInterval. The multiple thresholds and interval parameters allow for faster gain recovery. Typically, agcUnderRangeHighInterval could be set to gain update counter as shown in Figure 109. Therefore, when the signal level is below the mid and low thresholds, the recovery could happen multiple times within a single gain update counter, which makes the recovery much faster.
  • Page 127 Preliminary Technical Data UG-1828 The apdLowThresh has priority in terms of preventing recovery. If apdLowThresh reports an over range condition (sufficient signal peaks have exceeded its threshold in a gain update counter period), then no further recovery is allowed. apdLowThresh and hbUnderRangeHighThresh should be configured to be as close to the same value of dBFS, but assuming some small difference between the thresholds, then as soon as apdLowThresh is exceeded recovery will no longer occur.
  • Page 128 UG-1828 Preliminary Technical Data changed by larger amounts when the signal level is farther from the target level while make smaller gain changes when the signal is closer to the target level. This could allow the gain change faster when the level is farther away from the targeted range. Figure 111 shows the operation of the AGC when using the power detect.
  • Page 129 Preliminary Technical Data UG-1828 Peak Detect and Peak/Power Detect Mode Comparison Among the two detect modes, peak detect offers the quickest response time to overload signals by employing “fast attack” mode. It allows the AGC to respond within hundreds of nanoseconds in overload scenarios. In addition, the peak detect also provides “fast recovery” option to increase the gain of the desired signal quickly when an interferer disappears.
  • Page 130 UG-1828 Preliminary Technical Data properly, which can be done through API command. The feedback information can be configured into 2 modes, the peak detect mode and peak and power detect mode. In peak detect mode, the over-range and under-range conditions of both APD and HB detectors will be provided through DGPIO pins to user.

  • Page 131: Gain Control Detectors

    Preliminary Technical Data UG-1828 GAIN CONTROL DETECTORS In this section, three gain control detectors will be discussed in more details. Analog Peak Detector (APD) The analog peak detector is located in the analog domain following the TIA filter and prior to the ADC input (see Figure 105). It functions by comparing the signal level to programmable thresholds.
  • Page 132 UG-1828 Preliminary Technical Data Table 57. APD Attack and Recovery Step Sizes Gain Change Step Size Gain Attack apdGainStepAttack Gain Recovery apdGainStepRecovery Step size refers to the number of indices of the gain table the gain is changed. As explained earlier, the gain table is programmed with the largest gain in the Max Gain Index (typically index 255), with ever decreasing gain for decreasing gain index.
  • Page 133 Preliminary Technical Data UG-1828 The HB detector has a number of programmable thresholds. Some of these thresholds are only used in the fast recovery mode of the peak detect AGC configuration, as summarized in Table 58. Table 58. HB Overload Thresholds HB Threshold Usage hbHighThresh...

  • Page 134: Agc Clock And Gain Block Timing

    AGC CLOCK AND GAIN BLOCK TIMING The AGC clock is the clock which drives the AGC state machine. In ADRV9001 device, the default AGC clock (to support a set of standard sample rates) is at 184.32 MHz. When arbitrary sample rate is adopted in Rx, the AGC clock could vary.

  • Page 135: Analog Gain Control Api Programming

    Preliminary Technical Data UG-1828 IMMEDIATE GAIN ATTACK GAIN ATTACK TYPE 2 SLOW 5 AGC SLOW SLOW 5 AGC LOOP LOOP LOOP CLOCK GAIN UPDATE COUNTER CLOCK GAIN UPDATE COUNTER SETTLING SETTLING SETTLING CYCLE CYCLE DELAY DELAY DELAY DELAYED DELAYED GAIN GAIN RECOVERY RECOVERY...
  • Page 136 UG-1828 Preliminary Technical Data Figure 117 describes a high level flow chart of Rx gain control programming. Note the final step is to configure any GPIOs as necessary such as GPIO inputs which allow the AGC gain update counter to be synchronized to a slot boundary, or DGPIOs to directly control the gain index.
  • Page 137 Preliminary Technical Data UG-1828 adi_adrv9001_GainControlCfg_t +peakWaitTime +maxGainIndex +minGainIndex +gainUpdateCounter +attackDelay_us +slowLoopSettlingDelay +lowThreshPreventGainInc +changeGainIfThreshHigh +agcMode +resetOnRxon +resetOnRxonGainIndex +enableSyncPulseForGainCounter +enableFastRecoveryLoop +power +peak +extLna adi_adrv9001_PeakDetector_t adi_adrv9001_ExtLna_t adi_adrv9001_PowerDetector_t +powerEnableMeasurement +agcUnderRangeLowInterval +gpio +underRangeHighPowerThresh +agcUnderRangeMidInterval +powerDown +underRangeLowPowerThresh +agcUnderRangeHighInterval +settlingDelay +underRangeHighPowerGainStepRecovery +apdHighThresh +underRangeLowPowerGainStepRecovery +apdLowThresh +powerMeasurementDuration +apdUpperThreshPeakExceededCount +powerMeasurementDelay +apdLowerThreshPeakExceededCount +rxTddPowerMeasDuration +apdGainStepAttack...
  • Page 138 UG-1828 Preliminary Technical Data Default Parameter Description Min Value Value Value changeGainIfThreshHigh Applicable in both peak and peak and power detect modes. 0: Gain changes will wait for the expiry of the gain update counter if a high threshold count has been exceeded on either the APD or HB detector.
  • Page 139 Preliminary Technical Data UG-1828 Default Parameter Description Value Value Value powerMeasurementDelay Measurement delay to detect power for specific slice of gain update counter clock cycles rxTddPowerMeasDuration Following an Rx Enable, the power measurement block can 65535 be requested to perform a power measurement for a specific period of a frame.
  • Page 140 UG-1828 Preliminary Technical Data Default Value Parameter Description Min Value Value (TBD) agcUnderRangeHighInterval This sets the time constant (in AGC clock cycles) that the AGC will recover when the signal peaks are less than hbUnderRangeHighThresh. Calculated as (underRangeHighInterval+1) * underRangeMidInterval. Only applicable when the fast recovery option is enabled in Peak Detect AGC mode.
  • Page 141 Preliminary Technical Data UG-1828 Default Value Parameter Description Min Value Value (TBD) hbHighThresh This sets the upper threshold of the HB detector. 16383 13044 hbUnderRangeLowThresh This sets the lower threshold of the HB under range 16383 5826 threshold detectors. Used only when the fast recovery option of the peak detect AGC mode is being utilized.

  • Page 142: Digital Gain Control And Interface Gain (Slicer)

    External LNA Settling Delay A set of Rx gain control APIs are provided for user interaction with the ADRV9001 device. Some of them have been mentioned in the previous sections. The following table summarizes the list of API functions currently available with a brief description for each one. For more up-to-dated information and detailed descriptions, please refer to API doxygen document.
  • Page 143 Preliminary Technical Data UG-1828 The digital gain block is controlled by the Rx gain table as mentioned earlier. Note different digital gain will be applied when configured in gain correction or gain compensation mode. The Rx gain table has a unique front-end attenuator setting, with a corresponding amount of digital gain, programmed at each index of the table, as shown in Table 47.
  • Page 144 UG-1828 Preliminary Technical Data After applying the interface gain, the signal is provided to the data port in 16-bit format. The baseband processor could retrieve the interface gain through API commands to scale the power of the received signal to determine the power at the input to the device (or at the input to an external gain element if considered part of the digital gain compensation).

  • Page 145: Digital Gain Control And Interface Gain Api Programming

    Preliminary Technical Data UG-1828 from -36dB to 18dB and for WB applications, the interface gain is from −36 dB to 0 dB in 6 dB step size. This mode could be utilized especially when baseband processor input signal clipping is observed by the user. DIGITAL GAIN CONTROL AND INTERFACE GAIN API PROGRAMMING The API function adi_adrv9001_Rx_InterfaceGain_Configure() is provided to configure the interface gain.

  • Page 146: Usage Recommendations

    Gain Control Mode is selected as Automatic. When the Gain Control Mode is selected as Manual Pin or Manual SPI, it further enables the ADRV9001 internal signal detectors in either Peak Only or Peak and Power mode. By configuring the GPIO pins, user is allowed to retrieve the signal detector status which could be used to control Rx gain in Manual mode.
  • Page 147 Preliminary Technical Data UG-1828 relates to the selection of gain table. User should first select Rx gain table type at the bottom of this configuration page in TES.) The second section displays the current gain control mode. If AGC is configured as shown in Figure 123, users are not allowed to enter the other parameters in this section.
  • Page 148 UG-1828 Preliminary Technical Data Figure 124. TES Configuration for Rx Interface Gain, Signal Detection Parameters and Manual Control Mode Parameters (when MGC Pin is Configured) After finishing all the configurations, user could start the receive operations and observe the Rx gain changes. It is recommended to start from the default settings and change the parameters one by one as needed.

  • Page 149: Rx Demodulator

    RX NARROW-BAND DEMODULATOR SUBSYSTEM ADRV9001 Rx narrow-band demodulator subsystem, denoted by rxnbdem, is the digital baseband backend partition of ADRV9001 Rx channel. Note that narrow band, commonly for a wireless communication system, if the channel spacing, also known as channel bandwidth, is no more than 1 MHz, we call it “Narrowband System”.
  • Page 150 UG-1828 Preliminary Technical Data This frequency difference is named by the carrier frequency offset (CFO). The CFC in rxnbdem enables the BBIC to remove the CFO before the channel selection filtering at the receiver side. The correction value applied to the CFC, needs to be estimated and further input by the BBIC.
  • Page 151 Preliminary Technical Data UG-1828 profile onto the Rx Programmable FIR to perform common filtering. However, after the CFO is corrected via Carrier Frequency Corrector block, a tight filter profile can be loaded to perform the deep channel selection filtering. The change in the filter profile can be initiated by the BBIC on demand in the RF_Enabled State.

  • Page 152: Normal Iq Output Mode

    Round Module Round in rxnbdem is to map the ADRV9001 internal datapath bit-width to the Rx SSI output. This module cannot be bypassed. The Round module outputs 16-bit I data and 16-bit Q data to the Rx SSI output. If required, the Round module can output 16-bit I data to the Rx SSI output with the 16-bit output Q data set as ‘0’.

  • Page 153: Frequency Deviation Output Mode

    Low-pass filtering for smoothing the output FD signal Pulse Shaping Resampler Disable Enable for manual control Contact an Analog Devices Application Engineer for the specific filter profiles of Rx Programmable FIR and NB Programmable FIR. Rev. PrA | Page 153 of 253...

  • Page 154: Api Programming

    PFIR pointers are NULL. The ADRV9001 performs the PFIR coefficients switch for all channels that have new coefficients prepared and waiting when the API command adi_adrv9001_arm_Profile_Switch() is called. If ADRV9001 is in PRIMED state, the new coefficients will take effect on the next transition to RF_ENABLED.
  • Page 155 # PFIR_GAIN_0DB for i in range(pfir_dmr_12p5k.numCoeff): pfir_dmr_12p5k.coefficients[i] = pfir_dmr_12p5k_coeff[i] Adrv9001.arm.NextPfir_Set(1, pfir_fm_12p5k) # put in the right filter object Adrv9001.arm.Profile_Switch() NB Programmable FIR API Programming Same with Rx PFIR, a profile pre-defined set of NB PFIR coefficients (customized NB PFIR coefficients will be supported in the later software release) are automatically loaded during chip initialization, there is no need for baseband processor to call any PFIR coefficients loading API function.

  • Page 156: Power Saving And Monitor Mode

    ADRV9001 software adds additionally static and dynamic power saving schemes in order to extend the power saving feature to a broader market beyond DMR. ADRV9001 defines five extra power down modes that provides from low to high power saving but short to long recovery time, details will be introduced in the following section.

  • Page 157: Power-Down/Power-Up Channel In Calibrated State

    Calibrated state. Figure 134 shows a DMR radio switch from TX only frames into TX/RX alternate frames, ADRV9001 is initialized with Tx and Rx enabled, at the beginning of TX only frames, baseband processor can bring the RX channel into Calibrated State and power it down.
  • Page 158 UG-1828 Preliminary Technical Data TX ENABLE OFF TX ENABLE ON POWERING DOWN POWERING ON COMPONENTS BASED ON COMPONENTS BASED ON POWER SAVING MODE POWER SAVING MODE TX1 ENABLE RX ENABLE ON RX ENABLE OFF POWERING ON POWERING DOWN COMPONENTS BASED ON COMPONENTS BASED ON POWER SAVING MODE POWER SAVING MODE...

  • Page 159: Monitor Mode

    TX enable falling edge. Another option is user can power down more by using System Power Saving if the dark gray area is very long. User can set power down mode 3 to 5 to power down most of ADRV9001 components to save power and wake them up by DGPIO falling edge early enough before TX enable rising edge.
  • Page 160 } adi_adrv9001_MonitorDetectionMode_e; ADRV9001 can always buffer the latest incoming data in Monitor Mode detection cycle, once a valid incoming signal is detected and the baseband processor has been waked up by ADRV9001, ADRV9001 can send out the buffered Rx data to baseband processor. This procedure can make sure the baseband processor won’t miss the valid incoming signal when it’s in the sleep state.
  • Page 161 Preliminary Technical Data UG-1828 Mode, and these two modes can also be dynamically switched for different time slots, a System Power Saving or Monitor Mode API command should be sent during each time switching between System Power Saving. Rev. PrA | Page 161 of 253...

  • Page 162: Digital Predistortion

    Figure 139. Ideal Power Amplifier Output vs. Actual Power Amplifier Output ADRV9001 DPD FUNCTION The ADRV9001 device provides a fully integrated DPD function that supports both narrow-band (NB) and wide-band (WB) applications. It is a hardware/software combined solution which performs linearization of the power amplifier by pre-distorting the digital transmit signal with the inverse of the power amplifier’s nonlinear characteristics.

  • Page 163: Adrv9001 Dpd Supported Waveforms

    DPD. In FDD applications where only one Rx is used or in the TDD applications during Tx time slots, unused Rx can be used to perform DPD calibration as well as some other Tx tracking calibrations. Please refer to ADRV9001 Example Use Cases section for more details.

  • Page 164: Adrv9001 Dpd Performance

    CFR with an appropriate tradeoff between PAR reduction and EVM degradation before sending the transmit data to ADRV9001. It should be also noted that additional EVM degradation caused by the integrated DPD is negligible compared to the degradation caused by CFR.

  • Page 165: Dpd Configuration

    To use the integrated DPD properly and ensure optimal performance, user needs to configure DPD parameters properly. This could be done through ADRV9001 Transceiver Evaluation Software (TES) or Software Development Kit (SDK). The configuration consists of 2 sets of DPD parameters. The first set of DPD parameters is “pre initial calibration” parameters since they should be configured before performing initial calibration when the device is at the “STANDBY”...
  • Page 166 Selects the DPD model. “4” is the only allowed DPD model currently. User ADI_ADRV9001_DPD_MODEL_0 = 0, should always choose “4”. ADI_ADRV9001_DPD_MODEL_1 = 1, ADI_ADRV9001_DPD_MODEL_3 = 3, ADI_ADRV9001_DPD_MODEL_4 = 4, Model 4 is the ADRV9001 Model. Rev. PrA | Page 166 of 253...
  • Page 167 Preliminary Technical Data UG-1828 Parameter Type Description Default Note changeModelTapOrders bool Sets “TRUE” to use the model tap orders defined by FALSE The default model tap “modelOrdersForEachTap”. Set “FALSE” to ignore order for DPD Model 4 is: “modelOrdersForEachTap” and use the default order. [0] = 0x001F, [1] = 0x007F, [2] = 0x001F,...
  • Page 168 – 1 – 2 Figure 148. ADRV9001 DPD Model 4 LUT Configuration As shown in Figure 148, d(t) is the raw complex transmit (Tx) signal before predistortion. Its amplitude is the basis that the DPD actuator uses to predistort the d(t) via its LUT. The LUT consists of four taps, which are calculated with precomputed DPD coefficients...
  • Page 169 Preliminary Technical Data UG-1828 Tap 2: b = 1, b = 1, b = 1, b = 1, b = 1, b = 0, b = 0, b 2,2,0 2,2,1 2,2,2 2,2,3 2,2,4 2,2,5 2,2,6 2,2,7 Tap 3: b = 0, b = 1, b = 1, b = 1, b...
  • Page 170 UG-1828 Preliminary Technical Data preLutScale This value, given as a fixed point U2.1 number, sets the scaling factor before searching the LUT. The scaling factor can be set as 1, 1.5, 2, 2.5, 3 and 3.5. This allows the user to scale the input signal magnitude in order to cover close to the full range of the LUT for better DPD performance.
  • Page 171 Preliminary Technical Data UG-1828 Parameter Type Description Default Note immediateLutSwitching bool Determines whether the LUT TRUE FALSE not switches immediately or at currently the end of Tx data frame. supported. useSpecialFrame bool DPD only runs on a user FALSE Currently not indicated special frame.

  • Page 172: Board Configuration

    ADRV9001 Tx output to ORx input. User should measure this delay and provide it to ADRV9001 before initial calibration. The measured delay is then used to compensate the delay between x(t) and y(t).

  • Page 173: Dpd Api Programming

    Without filtering those harmonics, the DPD performance could be impacted. The step attenuators external to the ADRV9001 evaluation board are optional. Note it is important to set up the external loopback path before operating the integrated DPD.
  • Page 174 DPD can be considered as an adaptive filter which is modelled according to the behavior of the power amplifier. As mentioned earlier, the ADRV9001 default model (Model 4) consists of four taps. Each tap consists of a series of polynomial terms to fit the nonlinear behavior due to compression at higher output power.
  • Page 175 Preliminary Technical Data UG-1828 To find the best model tap order for a specific power amplifier design model, the user can take the following recommended procedures: Set the amplifier output power to have a compression ratio of 1 dB or slightly less, as shown in Figure 1, i.e. the maximum peak of the output signal is 1 dB below ideal linearity.

  • Page 176: General-Purpose Input/Output And Interrupt Configuration

    The Digital and Analog GPIO pins can be utilized as real-time status signals that provide device status information from ADRV9001 to the baseband processor when the GPIO pins are configured as outputs, with respect to ADRV9001. When set as inputs, the GPIO pins can be utilized as real-time control signals that can alter the device state.

  • Page 177: Digital Gpio Operation

    Each Digital GPIO pin can be set to either input or output mode, the input mode allows the baseband processor to drive pins on the ADRV9001 to execute specific tasks, the output mode allows the ADRV9001 to output various control or status signals to baseband processor.
  • Page 178 Normal and Monitor operation modes or wake up ADRV9001 from sleep state at the falling edge of “Mon_enable”.
  • Page 179 Input Control Out Mux Control Out Mux (sometimes referred as “Monitor out”) allows status signals within the ADRV9001 to be output to digital GPIOs, there are several types control out muxes as described below: Rx Control Out (Available for Rx1, Rx2) •...

  • Page 180: Tx Dclk Out

    UG-1828 Preliminary Technical Data detectors are provided to user. The other DGPIO configuration is for using the peak/power detect mode, in which the overrange and underrange conditions of APD and power detector are provided to user. The DGPIO pins could be associated with either one of the receivers, Rx1 or Rx2. However, when the similar information is required for both receivers, they could be selectively muxed and provided to user simultaneously.

  • Page 181: Interrupt

    RF Front-End Control To save the baseband processor control pins, ADRV9001 provides the function to output control signals via analog GPIO pins to power up/down the external RF front end components (i.e. LNA, TX Gain blocks, Ext PLL) or switch the T/R switch of a TDD system. For example, a TX_On, RX_ON output signal through the analog GPIOs and associated with the ADRV9001 internal work timing and state can be used to enable/disable the power amplifier and LNA respectively.
  • Page 182 AS THEY ARE PROCESSED RETURN STATUS REGISTER PRIOR TO CLEARING PLUS GP_INT MASK COMPLETE ANY FURTHER PROCESSING IF NECESSARY Figure 157. Sequence of Events Between Baseband Processor and ADRV9001 API with Respect to GP Interrupts Rev. PrA | Page 182 of 253...

  • Page 183: Auxiliary Converters And Temperature Sensor

    These features are included to simplify control tasks and reduce pin count requirements on the baseband processor by offloading these tasks to the ADRV9001. Example usage of the auxiliary converters include static voltage measurements performed by the AuxADC and flexible voltage control performed by the AuxDAC. This section outlines the operation of these features along with API command for configuration and control.

  • Page 184: Temperature Sensor

    ADI_ADRV9001_AUXADC3 The AuxADC clock rate is set to 30.72MHz (or close when ADRV9001 ARM system clock is changed) to get the best ADC performance. There are no on chip calibrations executed for the AuxADC, the ADC accuracy is limited to the accuracy of the supply reference. A simplified procedure for measuring and accounting for the AuxADC gain and offset error is performed, those AuxADC gain and offset errors are used to compensate the AuxADCs measure results.

  • Page 185: Rf Port Interface Information

    EXTERNAL LO PORTS: LO1± AND LO2± Two external LO inputs (LO1 and LO2) can be applied to ADRV9001 and each external LO signal can be used for any of two receivers or two transmitters instead of internally generated LO signal. AC-coupling interface is needed for both positive and negative sides of external LO input pins which are internally biased.
  • Page 186 S(3,3) = 0.136/–156.169 S(3,3) = 0.109/–125.024 IMPEDANCE = 77.425 – j8.680 IMPEDANCE = 86.866 – j15.742 –0.2 –5.0 –0.5 –2.0 –1.0 FREQUENCY (30.000MHz TO 6.000GHz) Figure 159. ADRV9001 RX A Port Series Equivalent Differential Impedance Rev. PrA | Page 186 of 253...
  • Page 187 Data Access Component (DAC). In the below diagram Term1 is the single ended input or output and Term2 represents the differential input or output RF port on ADRV9001. The Pi on the single ended side and the differential Pi configuration on the differential side allows maximum flexibility in designing matching circuits, and is suggested for all design layouts as it can step the impedance up or down as needed with appropriate component population.

  • Page 188: General Receiver Port Interface

    GENERAL RECEIVER PORT INTERFACE ADRV9001 has two independent receive input channels(Rx1 and Rx2). Both Rx channels can support up to 40MHz bandwidth and use differential signalling interface. The differential input signals would be applied to an integrated mixer. The mixer input pins are internally biased to 0.65 Volt and would need to be AC coupled depending on the common mode voltage level of the external circuit...

  • Page 189: General Transmitter Bias And Port Interface

    Figure 166. ADS Simulation Results of Return Loss Curve S parameters for a selected balun and ac-coupling SMD type caps and ADRV9001 RX input impedance can be used to represent balun’s balanced side interface to the device. Shunt and series matching component can be added with short TLs to represent possible PCB traces associated with these matching components on the single side of balun.
  • Page 190 Figure 169 to Figure 172 identify four basic differential transmitter output configurations. Impedance matching networks (balun single- ended port) are most likely to be required to achieve optimum device performance from ADRV9001. Also, the transmitter outputs must be ac-coupled in most applications due to the dc bias voltage applied to the differential output lines of the transmitter.
  • Page 191 1.8V Tx1_OUT+/ 1.8V Tx2_OUT+ Tx1 OR Tx2 OUTPUT STAGE Tx1_OUT–/ Tx2_OUT– 1.8V Figure 170. ADRV9001 RF Transmitter Interface Configuration B 1.8V Tx1_OUT+/ Tx2_OUT+ 1.8V Tx1 OR Tx2 OUTPUT STAGE Tx1_OUT–/ Tx2_OUT– 1.8V Figure 171. ADRV9001 RF Transmitter Interface Configuration C 1.8V...

  • Page 192: Impedance Matching Network Examples

    RX1A± and RX2A± Impedance Matching Network The ADRV9001 evaluation board utilizes both the top and bottom layers of the PCB evaluation platform to accommodate two balun footprints. The 0805 footprint accommodates the high frequency narrowband baluns while the backside accommodates the larger DB1627 case style transformer.
  • Page 193 Preliminary Technical Data UG-1828 BALUN LOCATED L245 ON BOTTOM OF THE BOARD T207 TCM2-33X+ C245 R245 L246 C246 R246 L247 L219 AGND L238 C238 R238 C247 C219 BALUN LOCATED RX2A_IN+ ON TOP L216 L236 OF THE BOARD RX2A R247 R219 0805 FOOTPRINT C216 C236...
  • Page 194 UG-1828 Preliminary Technical Data L/C/R 245 L/C/R 247 L/C/R 219 C232 L/C/R L/C/R L/C/R L/C/R L/C/R 246 L/C/R 248 L/C/R 220 R232 Frequency Balun L/C 218 L/C 221 625 MHz to Johanson L215: L216: L217: L238: L236: L245/246: L247/248: L218: L219/220: L221: C232:...
  • Page 195 Preliminary Technical Data UG-1828 Table 86. RX1B± and RX2B± Impedance Matching Network L/C/R L/C/R L/C/R 251 C233 L/C/R L/C/R L/C/R L/C/R L/C/R Frequency Balun L/C 222 L/C 224 L/C/R 252 L/C 225 L/C 229 R233 30 MHz to MiniCircuits L222: L223: L224: L226:...

  • Page 196: Receiver Rf Port Impedance Match Measurement Data

    UG-1828 Preliminary Technical Data L/C/R L/C/R L/C/R 251 C233 L/C/R L/C/R L/C/R L/C/R L/C/R Frequency Balun L/C 222 L/C 224 L/C/R 252 L/C 225 L/C 229 R233 4.5 GHz– 6 Johanson L217: L223: L224: L226: L237: L249/250: L251/252: L225: L227/228: L229: C233: 5400BL15B100...

  • Page 197: Transmitter Rf Port Impedance Matching Network

    TX1± and TX2± Impedance Matching Network For the TX path, the ADRV9001 evaluation board utilizes both the top and bottom layers of the PCB evaluation platform to accommodate two balun footprints. The 0805 footprint accommodates the high frequency narrowband baluns while the backside accommodates the larger AT224-1A case style transformer.
  • Page 198 UG-1828 Preliminary Technical Data Table 87. TX1± and TX2± Impedance Matching Network L/C/R C333 L309 C309 L339 C346/347 C334 L/C/R L/C/R L/C/R L/C/R Frequency Balun L/C 311 L310 C310 C339 R367/368 R361 C335 L/C 314 30 MHz to MiniCircuits L311: DNI L309/310: C309/ L312/313: L339:...

  • Page 199: Transmitter Rf Port Impedance Match Measurement Data

    Preliminary Technical Data UG-1828 L/C/R C333 L309 C309 L339 C346/347 C334 L/C/R L/C/R L/C/R L/C/R Frequency Balun L/C 311 L310 C310 C339 R367/368 R361 C335 L/C 314 2.8 GHz to Anaren L311: DNI L309/310: C309/ L312/313: L339: C346/347: R361: C333: L341: L348: L314:...

  • Page 200: External Lo Port Impedance Matching Network

    LO frequency. Method of obtaining matching network is similar to RX and TX port matching. Depending on the selected divide ratio of ADRV9001 external LO input frequency divider SPI register setting, a band of frequency in which external LO matching network need to operate should be correctly derived by the division ratio chosen.
  • Page 201 2nd order). The ADRV9001 provides special mode of operation for external LO in range from 500MHz to 1000MHz. In that region it is possible to inject external LO that will produce RF Channel frequency with x1 multiplier. For example:...
  • Page 202 UG-1828 Preliminary Technical Data R357 0Ω EXT_LO1+ C350 100pF L330 L327 L333 AGND R350 0Ω C320 C322 R322 T303 0Ω 0.001µF 100pF NCR2-123+ EXT_LO1– R326 0Ω C350 R310 R311 R356 0Ω R330 R331 L331 C352 L334 C353 100Ω 100Ω L332 L335 L329 LO1 IN/OUT...

  • Page 203: External Lo Impedance Match Measurement Data

    Preliminary Technical Data UG-1828 R356 L324 C349 L326 R321 L327/329 R326/327 L330/332 L331 L333/335 L334 C317 L325 C319 R320 C350/351 R324/325 C320/321 C352 C322/323 C353 Frequency Balun R308 R318 R309 R319 C357 R322/323 R328/329 R310/354 R330 R311/355 R331 R350 3 GHz to 6 L324: L325: L326:...

  • Page 204: Connection For External Device Clock (Dev_Clk_In)

    CONNECTION FOR EXTERNAL DEVICE CLOCK (DEV_CLK_IN) ADRV9001 can accommodate 3 different types of external clock signals applied at device clock input pins. A differential low voltage differential signalling (LVDS) clock signal or a single-ended clipped sinewave clock signal from a TCXO can be applied to the device input pins.

  • Page 205: Dev_Clk_In Phase Noise Requirements

    Preliminary Technical Data UG-1828 Device Clock Interface Modes LVDS 100nF CLOCK DEV_CLK_IN+ 100Ω 100nF DEV_CLK_IN– Figure 185. LVDS Interface Mode CMOS 100nF CLOCK DEV_CLK_IN+ DEV_CLK_IN– UNCONNECTED Figure 186. CMOS Interface Mode DEV_CLK_IN+ DEV_CLK_IN– Figure 187. Crystal (XTAL) Interface Mode FREQUENCY = 10.00MHz S(5,5) = 0.997/–402 IMPEDANCE = 9.694E3 + j2.467E4 FREQUENCY = 100.0MHz...

  • Page 206: Connection For Multichip Synchronization (Mcs) Input

    Clock source with phase noise performance outlined in Table 92 (or better) allows ADRV9001 to deliver datasheet performance. It should be noted that Table 92 provide reference information for ADRV9001 operating with LTE type standards. Each standard will determine its own DEV_CLK phase noise requirements. As an example, Table 93 provides recommendation for DEV_CLK when ADRV9001 is intended to operate with LMR type standards.

  • Page 207: Printed Circuit Board Layout Recommendations

    This section provides a checklist of issues to look for and guidelines on how to optimize the PCB to mitigate performance issues. The goal of this document is to help achieve the best possible performance from the ADRV9001 while reducing board layout effort.

  • Page 208: Fan-Out And Trace Space Guidelines

    FAN-OUT AND TRACE SPACE GUIDELINES The ADRV9001 device family uses a 196-pin BGA 12 × 12 mm package. The pitch between the pins is 0.8 mm. This small pitch makes it impractical to route all signals on a single layer. RF pins have been placed on the outer edges of the ADRV9001 package. This helps in routing the critical signals without a fan-out via.

  • Page 209: Component Placement And Routing Priorities

    COMPONENT PLACEMENT AND ROUTING PRIORITIES The ADRV9001 transceiver requires few external components to function, but those that are needed require careful placement and routing to optimize performance. This section provides a priority order and checklist for properly placing and routing critical signals and components as well as those whose location and isolation are not as critical.
  • Page 210 Optimization of RF transmission lines specific to the desired board environment is essential to the design and layout process. The ADRV9001 evaluation board uses microstrip lines for Rx and Tx RF traces. Some data port signal are routed using a •...
  • Page 211 Matching network design is explained in greater detail in the RF Port Interface Information section of this document. RF signal path isolation is critical to achieving the level of isolation specified in the ADRV9001 datasheet. More details on proper •...
  • Page 212 That trace should then be shielded with ground and provide power to ADRV9001 Power pin. A 1 µF capacitor should be placed near the power supply pin with the ground side of the bypass capacitor placed so that ground currents flow away from other power pins and their bypass capacitors.
  • Page 213 1.0 V analog, This approach that utilizes some of ADRV9001 internal LDOs to generate 1.0 V for internal blocks. For remining blocks it expect the 1.0 V to be delivered from external power source. Figure 196 outline power supply routing recommendations for this architecture.
  • Page 214 TRACE TO 1.8V DIG 4.7µF CAPACITOR Figure 196. ADRV9001 Power Supply Domains with Connection Guidelines, Some Internal LDOs bypassed, 1.0 V Analog Domain Required Ceramic 4.7 µF bypass capacitors must be placed at the VRFVCO2_1P0, VRFVCO1_1P0, VRX2LO_1P0, VRX1LO_1P0, VCLKVCO_1P0, VAUXVCO_1P0, VCONV_1P0 and VDIG_0P9 pins. Place these capacitors as close as possible to the device with the ground side of the bypass capacitor placed so that ground currents flow away from other power pins and their bypass capacitors if at all possible.

  • Page 215: Rf And Data Port Transmission Line Layout

    ALL DIGITAL GPIO SIGNALS ROUTED BELOW THE RED LINE Figure 197. ADRV9001 AuxADC, SPI, Analog GPIO/AuxDAC, MCS±, and Digital GPIO Signal Routing Guidelines RF AND DATA PORT TRANSMISSION LINE LAYOUT RF Line Design Summary The RF line design is a compromise between many variables. Line impedance, line to line coupling, and physical size represent the parameters subject to compromise.
  • Page 216 DIFFERENTIAL PI NETWORK Figure 198. Receiver Matching Network on ADRV9001 Evaluation Board The circuit in Figure 198 shows the layout topology for the chosen receiver matching network. Note the location and orientation of each component – placement is critical to achieve expected performance. Similarly, the circuit in Figure 199 shows the layout topology used for the transmitter matching network.
  • Page 217 Transmitter Bias and Port Interface This section considers the dc biasing of the ADRV9001 transmitter (Tx) outputs and how to interface to each Tx port. At full output power, each differential output side draws approximately 100mA of DC bias current. The Tx outputs are dc biased to a 1.8V supply voltage using either RF chokes (wire-wound inductors) or a transformer (balun) center tap connection.
  • Page 218 Each transmitter requires approximately 200mA supplied through an external connection. The PCB layout of the ADRV9001 board allows use of external chokes to provide 1.8V power domain to the ADRV9001 outputs to allow users to try different baluns that may not have a dc center tap pin to supply the bias voltage to the transmitter outputs.
  • Page 219 When a Tx balun that is able to conduct dc is used then the system shown in Figure 203 should be used. The decoupling cap near the Tx balun should be placed as close as possible to the balun’s DC feed pin. Its orientation should be perpendicular to the ADRV9001 device so the return current avoids a ground loop with the ground pins surrounding the Rx input.
  • Page 220 Figure 204. Transmitter Power Supply Using RF Chokes SSI Data Port Trace Routing Recommendations The Data Port interface transfer I/Q data between BBIC/FPGA and ADRV9001 Tx and Rx datapaths. There are two possible mode of operation for SSI data port: CMOS-SSI mode –...
  • Page 221 Evaluation Board FMC Connector Signals Mapping The ADRV9001 evaluation board utilize FMC standard connector as an interface to carrier boards. Table 95 outlines signal mapping utilized on FMC connector implemented on ADRV9001 evaluation board. Second column refers to FMC standard pinout names. For more information refer to ADRV9001 EVB schematic.

  • Page 222: Isolation Techniques Used On The Adrv9001 Evaluation Card

    ISOLATION TECHNIQUES USED ON THE ADRV9001 EVALUATION CARD Given the density of sensitive and critical signals, significant isolation challenges are faced when designing a PCB for the ADRV9001. Isolation requirements listed below were followed to accurately evaluate the ADRV9001 device performance. Analytically determining aggressor-to-victim isolation in a system is very complex and involves considering vector combinations of aggressor signals and coupling mechanisms.
  • Page 223 When utilizing the proposed isolating structures, it is important to place ground vias around the slots and apertures. Figure 206 illustrates the methodology used on the ADRV9001 evaluation card. When slots are used, ground vias should be placed at each end of the slots and along each side.
  • Page 224 UG-1828 Preliminary Technical Data I/O ports. Ground vias are used along single ended RF IO traces. Optimal via spacing is 1/10 of a wavelength, but that spacing can vary somewhat due to practical layout considerations. Figure 207. Shielding of Rx Launches RF IO baluns are spaced and aligned to reduce magnetic coupling from the structures in the balun package.

  • Page 225: Power Supply Recommendations

    Preliminary Technical Data UG-1828 POWER SUPPLY RECOMMENDATIONS TBD. Rev. PrA | Page 225 of 253...

  • Page 226: Adrv9001 Evaluation System

    ADRV9001 EVALUATION SYSTEM The ADRV9001 family demonstration system enables customers to evaluate the device without having to develop custom software or hardware. The system is comprised of a radio daughtercard, an Xilinx ZYNQ ZC706 motherboard, an SD card with operating system, a 12 V power supply for the ZYNQ ZC706 that connects to a wall outlet, and a C#-based evaluation software application.
  • Page 227 Preliminary Technical Data UG-1828 Figure 208. Xilinx ZC706 ZYNQ Evaluation Board with Jumper Settings and Switch Position Configured to Work with ADRV9001 Evaluation Platform Rev. PrA | Page 227 of 253...
  • Page 228 Figure 209. ADRV9001 Evaluation Card and ZYNQ ZC706 Evaluation Platform with Connections Required for Testing The ADRV9001 evaluation system utilizes a Linux operating system. Linux requires time to boot up as well as soft shut down before hardware power off. The user is expected to use the software power off feature or press the SW9 button on the ZYNQ ZC706 evaluation platform before physically switching power off using SW1.

  • Page 229: Hardware Operation

    • For receiver testing on the ADRV9001 evaluation card, use a clean signal generator with low phase noise to provide an input signal to the selected receiver RF input. Use a shielded RG-58, 50 Ω coaxial cable (1 m or shorter) to connect the signal generator.

  • Page 230: Transceiver Evaluation Software (Tes)

    Figure 212. Software Installation Directory Starting the Transceiver Evaluation Software User can start the TES by clicking on Start -> ADRV9001 Transceiver Evaluation Software. Figure 213 shows the opening page of the TES after it is activated. Rev. PrA | Page 230 of 253...
  • Page 231 Please contact the ADI Applications Engineering team if the ADRV9001 Evaluation System needs to operate over a remote connection and a different IP address for the Xilinx ZYNQ platform is desired.
  • Page 232 UG-1828 Preliminary Technical Data Figure 214. Setup Revision Information Configuring the Device Contained within the Device Configuration tab are setup options for the device. In this page the user can select the following: • Product: • Currently only ADRV9002 is supported •...
  • Page 233 Preliminary Technical Data UG-1828 Figure 215. Device Configuration Tab In the Board Configuration tab, there are settings for transmitter External Loopback. This is typically used for DPD type applications. The user can either enable and disable the external loopback after power amplifier. If it is enabled, the user should enter the expected loopback peak power in the Peak Power entry.
  • Page 234 UG-1828 Preliminary Technical Data Figure 217. Board Configuration Tab Initialization The Initialization tab (see Figure 218 and Figure 219) provides access to the settings that determine device startup configuration. This page allows the user to: • Set the device clock. •...
  • Page 235 The receiver Gain Control tab (Figure 220) allows user to configure per channel, receiver gain control mode. Configuration selected in that tab is then applied to the ADRV9001 during initialization. During runtime user can change interface gain as well as if manual mode is enabled Rx gain.
  • Page 236 Filters ADRV9001 evaluation software allows users to specify their own custom programmable filter for the receiver. This filter is up to 128 taps. The custom filter has to be in the format of csv or txt file and coefficients need to be 24-bit signed integers.
  • Page 237 Rx and Tx Overview The “Rx Overview” (Figure 223) and “Tx Overview” (Figure 224) tabs aim to provide more detail on ADRV9001 selected mode of operation using “Device Configuration” tab (Figure 215). The Rx and Tx datapath overview diagrams are provided in each tab. These...
  • Page 238 UG-1828 Preliminary Technical Data tabs provide user with read back of ADC/DAC sampling frequencies, analog filtering configuration, datapath sampling rate, data port format, mode of operation and sampling rate. In “Rx Overview” tab (Figure 223) user can also read back IF frequency and observe pFIR channel filtering characteristics and their passband flatness.

  • Page 239: Transmitter Operation

    Preliminary Technical Data UG-1828 Figure 224. Tx Overview Tab Other Functionalities Under File menu there are: Save Session and Load Session options which allow save and restore TES configuration parameters, • Generate Profile File provides option to create JSON type profile configuration file. •...
  • Page 240 • Pressing the play symbol moves the ADRV9001 to the transmit state and starts a process where selected Data Files for the “Tx1” and “Tx2” are sent to the ADRV9001. The data is then stored on the Xilinx ZYNQ motherboard RAM and the RAM pointer loops through the data continuously until the stop button is pressed.
  • Page 241 Preliminary Technical Data UG-1828 The length of TX transmit data should be multiple of 64. data file will be played continuously, therefore the data should be phase continuous. Real | Imaginary ----------|----------- | Q1 | Q2 | Q3 | Q4 Rev.

  • Page 242: Receiver Operation

    UG-1828 Preliminary Technical Data RECEIVER OPERATION The Receive tab opens a window as shown in Figure 226. The upper plot displays the FFT of the received input data and the lower plot shows its time domain waveform. When multiple Rx inputs are enabled, the user can select the desired data to be displayed in the Spectrum plot using the checkboxes below the plot.
  • Page 243 Preliminary Technical Data UG-1828 Figure 226. Receive Data Tab Rev. PrA | Page 243 of 253...
  • Page 244 Go to IronPython, select Build and then select Run. This function executes Iron Python script open in currently active script tab using ADRV9001 evaluation hardware. Script output is displayed in bottom side of the Iron Python script tab. For this example, the Tx attenuation for the selected channel changes.

  • Page 245: Time Division Duplexing (Tdd)

    TIME DIVISION DUPLEXING (TDD) ADRV9001 supports automatic TDD operation. User can send and receive TDD framed data by configuring this tab. This of course depends on how system and setup is selected described in the previous sections. ADRV9001 comes with predefined timing configurations by default.
  • Page 246 UG-1828 Preliminary Technical Data Figure 229. TDD Configuration Tab TRACKING CALIBRATIONS Tracking calibration algorithms can be enabled/disabled in the tracking cal tab. Certain algorithms can only be enabled in certain profiles. For example RX harmonic distortion can only be enabled if it is configured in DMR, Analog FM, and Tetra profiles. It grays out and is disabled in LTE and custom profiles.
  • Page 247 AUXILIARY DAC/ADC ADRV9001 evaluation software allows user for setting Auxiliary ADC/DAC for different control or monitoring purposes. User can go to Auxiliary tab and enable Aux DAC/ADC here. For Aux DACs, user needs to specify a DAC code, valued from 0 ~ 4095. This effectively sets the voltage level for that Aux DAC pin.
  • Page 248 POWER MONITORING The ADRV9001 evaluation software allows user to monitor power usage of the system. On top there is a button Power Monitoring, which shows detailed voltage, current and power status of each power domain. Below is a screenshot of the power monitor window.
  • Page 249 Preliminary Technical Data UG-1828 POWER SAVINGS AND MONITOR MODE User can specify certain power saving mode in this tab. We divide power saving modes to two categories. System Power Savings and Channel Power Savings. System Power Savings include CLKPLL, LDO and ARM power down. These can be controlled via DGPIO pins. Channel Power Savings include RF PLL and LDO power down.
  • Page 250 UG-1828 Preliminary Technical Data Figure 235. Power Savings and Monitor Mode LOG FILE On top of the GUI, there is a button Log File, which shows logging information of the system. If the PC is connected to the evaluation platform, log file will show the version numbers for different component of the system, including firmware, FPGA, API etc. If errors occur, for example programming the chip fails, log file will provide certain debugging information on what is failing.
  • Page 251 Check if the board is properly powered. There should be 12V present at the J22 input, and after powering the ZYNQ platform on (SW1 turned on) the following should be true: Fan on the ZYNQ platform is activated. Ensure that fan cable is reconnected to ADRV9001 evaluation platform fan header P702.
  • Page 252 Orange LED Blinks Constantly The ZYNQ ZC706 generated power domain for IOs that control ADRV9001 over FMC interface. That power domain is called VADJ. For proper operation voltage on that power domain should not exceed 1.89V. The SD card provided together with an evaluation card ensures that VADJ is properly set.
  • Page 253 Legal Terms and Conditions Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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