Analog Devices ADRV9005 Reference Manual page 75

Reference Manual
DATA INTERFACE
An optional LVDS port (alternative function of Digital GPIO) can also be configured as an output LVDS pad used as a reference clock
TX_DCLK_OUT (±) for the baseband processor. Use TX_DCLK_OUT to generate the LSSI clock, strobe, and data signal.
Transmit LSSI with Separate Lanes for I and Q
Figure 55 shows the transmit LSSI (Tx1 and Tx2) for a 16-bit I/Q data sample with MSB first configuration.
Figure 56 shows the transmit LSSI (Tx1 and Tx2) for a 12-bit I/Q data sample with MSB first configuration.
The TX_STROBE signal is aligned with the first bit of the serialized data (I and Q), and can be configured to be high:
For a half-clock cycle at the start of the I and Q sample transmit. For a 16-bit data sample, the TX_STROBE is high for a half-clock cycle and
►
low for a half and 15 clock cycles. For a 12-bit data sample, the TX_STROBE is high for a half-clock cycle and low for a half and 11 clock
cycles.
For half of I and Q data duration. For a 16-bit data sample, the TX_STROBE is high for 4 clock cycles, and low for 4 clock cycles (Q data
►
sample). For a 12-bit data sample, the TX_STROBE is high for 3 clock cycles and low for 3 clock cycles.
In the 12-bit I/Q mode, 12-bit samples from LSSI are extended to 16 bits by padding four bits zero in LSB for the following transmit datapath
process.
Transmit LSSI with One-Lane for I and Q
In this mode, only one-lane is used to transfer I and Q data samples. The I/Q data bits can be deserialized with configurable I or Q first and
MSB or LSB first. The strobe signal can be configured to high for a half-clock cycle to indicate the start of the I and Q symbols or for half of the I
and Q data duration to distinguish between I and Q data.
Figure 57 shows the one-lane LSSI (Tx1 and Tx2) for a 16-bit I/Q data sample with I sample and MSB first configuration.
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Figure 55. Transmit LSSI Timing for 16-Bit I/Q Data Sample on Separate Lanes
Figure 56. Transmit LSSI Timing for 12-Bit I/Q Data Sample on Separate Lanes
ADRV9001
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