Receiver/Observation Receiver Signal Chain - Analog Devices ADRV9005 Reference Manual

Reference Manual

RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN

The ADRV9001 offers dual receive channels. With a minimum number of external components, each receive channel builds a complete
RF-to-bits signal chain, which serves as RF front end for a wide range of applications. It supports both the time division duplex (TDD) and
frequency division duplex (FDD) modes, and receives both narrowband (NB) and wideband (WB) signals up to 40 MHz. NB applications include
DMR, P25, and TETRA, while WB applications are geared towards LTE transmissions. For example, the ADRV9001 supports standard sample
rates of 24 kHz (typically for FM waveforms), 144 kHz and 288 kHz (typically for TETRA signals), and 1.92 MHz, 3.84 MHz, 7.68 MHz, 15.36
MHz, 30.72 MHz, and 61.44 MHz (typically for LTE signals). Besides these standard rates, the ADRV9001 also supports an almost continuous
range of sample rates between 24 kHz and 61.44 MHz. Some sample rates are not supported due to internal clocking constraints.
Figure 146 describes the top-level structure of the ADRV9001 receivers.
major subsystems, the analog front end (AFE) and digital front end (DFE). The AFE subsystem contains four major components: programmable
front end attenuator, matched I and Q mixer, low-pass filter (LPF), and analog-to-digital converter (ADC). The attenuators control the signal
gain to avoid overloading the datapath when a strong signal interferes. It is followed by the mixers to down convert the received signals
for digitization. The output current of the mixers is further converted to voltage and filtered by the LPFs before passing to the ADCs. The
ADRV9001 provides two pairs of ADCs, a pair of high performance (HP) ADCs to achieve high linearity performance and a pair of low power
(LP) ADCs with slightly less linearity performance but significant lower power consumption. This design allows a flexible trade-off between
power consumption and linearity performance.
The DFE subsystem contains a series of digital signal processing components such as sample rate decimation (DEC), DC offset correction
(DC), quadrature error correction (QEC), digital down conversion (DDC) with numerically controlled oscillator (NCO), a programmable 128-tap
FIR filter (PFIR), receiver signal strength indicator (RSSI), frequency offset correction (FOC), phase offset correction (POC), and overload
detectors. The DEC decimates the ADC sample rate to the desired output sample rate. The DC, QEC, PFIR, FOC, and POC condition the
digital signals at different stages of the datapath for optimal performance.
The overload detectors are used for gain control in the datapath. The RSSI provides signal power measurement to control the bit-width of the
output signal. In addition, it detects the presence of a signal in a desired frequency band. At the end of the signal chain, through CMOS-SSI or
LVDS-SSI data port, the output signal is delivered to the based band processor for further processing.
The ADRV9001 supports an RF LO range from 30 MHz to 6 GHz. The RF LOs are generated through two internal phase lock loops (PLL)
or applied externally to the part. The digital subsystem contains an optional digital mixer driven by a programmable NCO. The receiver LO
can offset from the frequency of the desired channel and then make use of the digital mixer to down convert the signal to baseband before
being processed by the baseband processor. There are several advantages to offset the receiver LO from the frequency of the desired channel:
impairments that exist around the receiver LO, such as LO-leakage, can be avoided. The effect of flicker noise from the baseband circuits can
be mitigated because the received signal is offset from DC in the analog signal path. Also, image rejection can be improved if the receiver LO
is offset sufficiently far from the desired channel, such that the image frequency lies in the attenuation region of the external RF filter. The IF
operation works with both NB and WB applications. Typically, when the receiver is operating in the NB mode, the sensitivity requirements for
these applications demand very low noise performance. Therefore, the intermediate frequency (IF) approach is preferred. When the receiver is
operating on a WB signal, it uses direct down conversion or zero IF (ZIF) (although IF approach is also available for WB signal). In this mode,
the DDC is bypassed.
Figure 147 describes the simplified transmit and receive signal path between the antenna and the ADRV9001 device. The components
between the antenna and the ADRV9001 device are external components. In the transmit path, typically, the output signal from the device goes
through a variable gain amplifier (VGA), a low-pass filter (LPF), and a power amplifier before transmitting through antenna. In the receive path,
typically, the RF signal receiving from the antenna goes through a low noise amplifier (LNA) and a band-pass filter (BPF) before sending to the
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Figure 146. Top Level Structure of ADRV9001 Dual Receiver
Figure 146 shows that each receiver path Rx1 or Rx2 contains two
ADRV9001
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