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ADRV9001 System Development User Guide for the RF Agile Transceiver Family
ADRV9001 SYSTEM DEVELOPMENT USER GUIDE OVERVIEW
The ADRV9001 system development user guide covers the following:
ADRV9002
►
ADRV9003
►
ADRV9004
►
ADRV9005
►
ADRV9006
►
The ADRV9001 is the part number designation used throughout this user guide to refer to all products comprising the ADRV9001 family shown
above. Some family members do not include all the features or functions. For each feature and function, refer to the individual product data
sheet. A synopsis of the main differentiators is also given in
analog.com
Table
1.
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND
LEGAL TERMS AND CONDITIONS.
Reference Manual
ADRV9001
Rev. A | 1 of 377
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Table of Contents
Related Manuals for Analog Devices ADRV9005
Summary of Contents for Analog Devices ADRV9005
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Page 1: Adrv9001 System Development User Guide Overview
► ADRV9003 ► ADRV9004 ► ADRV9005 ► ADRV9006 ► The ADRV9001 is the part number designation used throughout this user guide to refer to all products comprising the ADRV9001 family shown above. Some family members do not include all the features or functions. For each feature and function, refer to the individual product data sheet. -
Page 2: Table Of Contents
SPI Test ............61 ADRV9002 ............9 SPI Main............61 ADRV9003 ............11 Data Interface............64 ADRV9004 ............11 General Description .........64 ADRV9005............11 Electrical Specification........64 ADRV9006............11 CMOS Synchronous-Serial Interface ADRV9001 Product Family Comparison..12 (CMOS-SSI)........... 66 ADRV9001 Example Use Cases......13 LVDS Synchronous-Serial Interface (LVDS- ADRV9001 in a Single-Band 2T2R FDD SSI).............. - Page 3 Reference Manual ADRV9001 TABLE OF CONTENTS Frequency Hopping Timing ......125 ADRV9001 DPD Function......230 Additional Frequency Hopping Operations..132 ADRV9001 DPD Supported Waveforms..231 Diversity Mode..........136 DPD with Frequency Hopping (FH)....232 Frequency Hopping with Rx/ORx Gain ADRV9001 DPD Performance ...... 232 Control............137 Closed Loop Gain Control (CLGC)....233 Special Frequency Hopping Operations..137...
- Page 4 REVISION HISTORY 8/2024—Rev. 0 to Rev. A Changes to ADRV9001 System Development User Guide Overview Section..........1 Added ADRV9005 Section..........................11 Added ADRV9006 Section..........................11 Added ADRV9001 Product Family Comparison Section and Table 1; Renumbered Sequentially....12 Changes to API Initialization Sequence Section....................46 Changes to Warm Boot Section and Table 15....................
- Page 5 Reference Manual ADRV9001 TABLE OF CONTENTS Added Dual Hopping Tables Section......................124 Change to Figure 113..........................125 Added Dual Hop Timing Section and Figure 119..................128 Changes to PLL Retune Section and Figure 120..................129 Replaced Table 54............................129 Added Table 55............................129 Added PLL Retune Measurement Section, Figure 121 to Figure 123............
- Page 6 Reference Manual ADRV9001 TABLE OF CONTENTS Changes to Figure 301..........................317 Moved LDO Configurations Section, Figure 305 to Figure 307, and Table 127 to Table 130...... 322 Changes to Hardware Setup (ZYNQ ZC706) Section and Figure 308............329 Added Figure 309............................330 Changes to Hardware Setup (ZCU102) Section and Figure 312..............331 Added Figure 313............................
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Page 7: How To Use This Document
Reference Manual ADRV9001 HOW TO USE THIS DOCUMENT Figure 1. Flowchart for Document Navigation analog.com Rev. A | 7 of 377... -
Page 8: Block Diagram
Reference Manual ADRV9001 BLOCK DIAGRAM Figure 2. ADRV9002 Block Diagram analog.com Rev. A | 8 of 377... -
Page 9: Product Highlights
Reference Manual ADRV9001 PRODUCT HIGHLIGHTS ADRV9002 ADRV9002 delivers a versatile combination of high performance and low power consumption required by battery-powered radio equipment. It can operate in both the frequency division duplex (FDD) and time division duplex (TDD) modes. The ADRV9002 operates from 30 MHz to 6000 MHz, which covers the very high frequency (VHF), licensed and unlicensed cellular bands, and industrial, scientific, and medical (ISM) bands. - Page 10 Reference Manual ADRV9001 PRODUCT HIGHLIGHTS For sample rates above 2.5 MHz, single channel data is serialized over four lanes with two additional lanes required for a clock (SDR or DDR) and a frame synchronization signal, which supports a maximum sample rate of 20 MHz. The LVDS electrical interface supports two modes of operation.
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Page 11: Adrv9003
ADRV9002 transceiver. The differences between the ADRV9002 and the ADRV9005 are the following: RF IOs. The ADRV9005 has one receiver and one transmitter. ► Tx Tracking calibrations can only be performed in TDD mode. Not available in FDD mode. -
Page 12: Adrv9001 Product Family Comparison
Closed Loop Gain Control Monitor Mode Power Saving Modes ADC Option HP/LP HP/LP HP/LP HP/LP External LO Option ADRV9005 can support Tx tracking cals when configured for TDD profiles. Not available during FDD operation. analog.com Rev. A | 12 of 377... -
Page 13: Adrv9001 Example Use Cases
Reference Manual ADRV9001 ADRV9001 EXAMPLE USE CASES The section provides an overall idea on how an ADRV9001 integrated transceiver can operate as an RF front end in different applications. The list is not exhaustive, and there are other applications the ADRV9001 can serve. Each example is accompanied with a table that explains the main limitations and highlights when implementing the ADRV9001 in the end application. - Page 14 Reference Manual ADRV9001 ADRV9001 EXAMPLE USE CASES Table 2. Constraints and Limitations in a Single-Band 2T2R FDD Type Small-Cell Application (Continued) Functionality Constraints and Limitations Transmitter Signal Path Ensure an appropriate level of isolation between Tx1 and Tx2 as well as receiver to transmitter at the system level. LO Generation In FDD type small-cell applications, the ADRV9001 can use its internal LO to generate RF LO1 for uplink (Rx1 and Rx2) and RF LO2 for downlink (Tx1 and Tx2).
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Page 15: Adrv9001 In A Dual-Band 2T2R Fdd Type Small-Cell Application
Reference Manual ADRV9001 ADRV9001 EXAMPLE USE CASES ADRV9001 IN A DUAL-BAND 2T2R FDD TYPE SMALL-CELL APPLICATION Figure 4. ADRV9001 in a Dual-Band 2T2R FDD Type Small-Cell Application Dual-Band 2T2R FDD Overview With a minimum number of external components, the ADRV9001 transceiver can be used to build a complete dual and RF-to-bits signal chain that can serve as RF front end in small-cell type applications. - Page 16 Reference Manual ADRV9001 ADRV9001 EXAMPLE USE CASES Table 3. Constraints and Limitations in a Dual-Band 2T2R FDD Type Small-Cell Application Functionality Constraints and Limitations Receiver Signal Path Ensure an appropriate level of isolation between Rx1 and Rx2 as well as receiver to transmitter at the system level. In the previous example, RxB inputs are used to work with receiver Band B signals as well as during initialization calibrations.
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Page 17: Adrv9001 In A Single-Band 2T2R Tdd Type Small-Cell Application
Reference Manual ADRV9001 ADRV9001 EXAMPLE USE CASES ADRV9001 IN A SINGLE-BAND 2T2R TDD TYPE SMALL-CELL APPLICATION Figure 5. ADRV9001 in a Single-Band 2T2R TDD Type Small-Cell Application Single-Band 2T2R TDD Overview With a minimum number of external components, the ADRV9001 transceiver can be used to build a complete RF-to-bits signal chain that can serve as RF front end in TDD type small cell type applications. - Page 18 Reference Manual ADRV9001 ADRV9001 EXAMPLE USE CASES Table 4. Constraints and Limitations in a Single-Band 2T2R TDD Type Small-Cell Application (Continued) Functionality Constraints and Limitations RF Front End For LO generation, the ADRV9001 uses internal VCO that generates a square wave type signal. A square wave LO produces harmonics. For example, depending on RF matching used on the RF ports, the second LO harmonic can be as high as −50 dBc, and the third harmonic can be as high as −9 dBc.
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Page 19: Adrv9001 In 1T1R Fdd With Dpd Type Application
Reference Manual ADRV9001 ADRV9001 EXAMPLE USE CASES ADRV9001 IN 1T1R FDD WITH DPD TYPE APPLICATION Figure 6. ADRV9001 in 1T1R FDD with DPD Type Application 1T1R FDD with DPD Overview With a minimum number of external components, the ADRV9001 transceiver can be used to build a complete RF-to-bits signal chain that can serve as RF front end in FDD type applications that require DPD. - Page 20 Reference Manual ADRV9001 ADRV9001 EXAMPLE USE CASES Table 5. Constraints and Limitations in 1T1R FDD with DPD Type Application (Continued) Functionality Constraints and Limitations as high as −9 dBc. Therefore, the RF filtering on the receiver and transmitter path must ensure that signals at the LO harmonic frequencies (up to ninth in some cases) do not affect overall system performance.
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Page 21: Adrv9001 In A Tetra Type Portable Radio Application
Reference Manual ADRV9001 ADRV9001 EXAMPLE USE CASES ADRV9001 IN A TETRA TYPE PORTABLE RADIO APPLICATION Figure 7. ADRV9001 in a TETRA Type Portable Radio Application TETRA Type Portable Radio Overview With a minimum number of external components, the ADRV9001 transceiver can be used to build a complete RF-to-bits signal chain that can serve as RF front end in TETRA type applications. - Page 22 Reference Manual ADRV9001 ADRV9001 EXAMPLE USE CASES Table 6. Constraints and Limitations in a TETRA Type Portable Radio Application (Continued) Functionality Constraints and Limitations the transmitter observation is also used by the transmitter tracking calibrations. In case of external DPD, ensure that access to the receiver path during transmitter slots is time-shared between the external DPD operation and transmitter calls.
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Page 23: Adrv9001 In A Dmr Type Portable Radio Application
Reference Manual ADRV9001 ADRV9001 EXAMPLE USE CASES ADRV9001 IN A DMR TYPE PORTABLE RADIO APPLICATION Figure 8. ADRV9001 in a DMR Type Portable Radio Application DMR Type Portable Radio Overview With a minimum number of external components, the ADRV9001 transceiver can be used to build a complete RF-to-bits signal chain that can serve as RF front end in DMR type applications. - Page 24 Reference Manual ADRV9001 ADRV9001 EXAMPLE USE CASES Table 7. Constraints and Limitations in a DMR Type Portable Radio Application (Continued) Functionality Constraints and Limitations Calibrations During the receiver initialization sequence, ensure there are no signals present at the receiver input (external LNA must be disabled), and appropriate termination must be present at the LNA output to avoid reflections of the receiver calibration tones.
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Page 25: Adrv9001 In An Fdd Type Repeater Application
Reference Manual ADRV9001 ADRV9001 EXAMPLE USE CASES ADRV9001 IN AN FDD TYPE REPEATER APPLICATION Figure 9. ADRV9001 in an FDD Type Repeater Application with Baseband Processor Analyzing Traffic Data ADRV9001 in an FDD Type Repeater Application with Baseband Processor With a minimum number of external components, the ADRV9001 transceiver can be used to build a complete RF-to-bits signal chain that can serve as RF front end in repeater or frequency translator type applications. - Page 26 Reference Manual ADRV9001 ADRV9001 EXAMPLE USE CASES Table 8. Constraints and Limitations in an FDD Type Repeater Application with Baseband Processor Analyzing Traffic Data (Continued) Functionality Constraints and Limitations as high as −9 dBc. Therefore, the RF filtering on the receiver and transmitter path must ensure that signals at the LO harmonic frequencies (up to ninth in some cases) do not affect overall system performance.
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Page 27: Adrv9001 In An Fdd Type Repeater Application Using Internal Loopbacks
Reference Manual ADRV9001 ADRV9001 EXAMPLE USE CASES ADRV9001 IN AN FDD TYPE REPEATER APPLICATION USING INTERNAL LOOPBACKS Figure 10. ADRV9001 in an FDD Type Repeater Application Without Baseband Processor Analyzing Traffic Data FDD Type Repeater Using Internal Loopbacks With a minimum number of external components, the ADRV9001 transceiver can be used to build a complete RF-to-RF signal chain that can serve as a repeater or a frequency translator. - Page 28 Reference Manual ADRV9001 ADRV9001 EXAMPLE USE CASES Table 9. Constraints and Limitations in an FDD Type Repeater Application Without Baseband Processor Analyzing Traffic Data (Continued) Functionality Constraints and Limitations RF Front End For LO generation, the ADRV9001 uses internal VCO that generates square wave type signal. A square wave LO produces harmonics. For example, depending on RF matching used on the RF ports, the second LO harmonic can be as high as −50 dBc, and the third harmonic can be as high as −9 dBc.
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Page 29: Adrv9001 In A Tdd Type Repeater Application
Reference Manual ADRV9001 ADRV9001 EXAMPLE USE CASES ADRV9001 IN A TDD TYPE REPEATER APPLICATION Figure 11. ADRV9001 in a TDD Type Repeater Application with Baseband Processor Analyzing Traffic Data TDD Type Repeater Overview With a minimum number of external components, the ADRV9001 transceiver can be used to build a complete RF-to-bits signal chain that can serve as RF front end in TDD type repeater or frequency translator applications. - Page 30 Reference Manual ADRV9001 ADRV9001 EXAMPLE USE CASES Table 10. Constraints and Limitations in a TDD Type Repeater Application with Baseband Processor Analyzing Traffic Data Functionality Constraints and Limitations LO Generation In the TDD type repeater application, the ADRV9001 can use its internal LO to generate RF LO1 for both uplink and downlink. It is also possible to use external LO inputs in this mode of operation.
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Page 31: Adrv9001 In A Radar Type Application
Reference Manual ADRV9001 ADRV9001 EXAMPLE USE CASES ADRV9001 IN A RADAR TYPE APPLICATION Figure 12. ADRV9001 in a Radar Type Application Radar Type Application Overview With a minimum number of external components, the ADRV9001 transceiver can be used to build a complete RF-to-bits signal chain that can serve as RF front end building block in Radar type applications. - Page 32 Reference Manual ADRV9001 ADRV9001 EXAMPLE USE CASES external DSA in the receiver signal chains. For time-critical TDD type applications, the ADRV9001 transceiver can be controlled by toggling control lines. The ADRV9001 can control external receiver/transmitter switch using its analog GPIOs as well as provide power amplifier bias voltage using AuxDAC outputs.
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Page 33: Software System Architecture Description
SOFTWARE SYSTEM ARCHITECTURE DESCRIPTION This section provides information about the device driver application programming interface (API) software developed by Analog Devices for the ADRV9001 transceivers. It also outlines the overall architecture, folder structure, and methods to use the API software on the user platform. -
Page 34: Folder Structure
Figure 15. Each subfolder is explained in the following sections. Analog Devices understands that the developer may want to use a different folder structure. Although Analog Devices provides the ADRV9001 API source code releases in the folder structure shown in... -
Page 35: Customizing The System Architecture And File Structure
Do not modify the files contained in the /ADRV9001 or other devices in this section. There is no software support when these files are modified. Analog Devices maintains this code. The only exception is that the user can modify #define macros in adi_ADRV9001_user.h, such as modifying polling timeouts and interval settings for various functions. - Page 36 The adi_platform.c file is where the HAL is chosen. For the default HAL provided by Analog Devices, it is also implemented in the adi_platform.c file. However, make no edits to the default HAL stored under linux_uio\. Users have placeholder files in the customer\ folder.
- Page 37 Reference Manual ADRV9001 SOFTWARE SYSTEM ARCHITECTURE DESCRIPTION Figure 17. API Folder Structure with Customer Interaction Points Highlighted More details are provided in the customer\ folder in the Software Integration chapter, which goes into more specifics on the HAL. At this point of development, read the files under the highlighted directories in Figure 17 (primarily the customer\ folder) before editing them.
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Page 38: Software Integration
Reference Manual ADRV9001 SOFTWARE INTEGRATION The ADRV9001 API package was developed using the ZC706 or ZCU102 Evaluation platform. This section describes how to use the ADRV9001 API in a custom hardware/software environment. This is readily accomplished because the API was developed abiding by C99 constructs while maintaining Linux system call transparency. - Page 39 Reference Manual ADRV9001 SOFTWARE INTEGRATION #include "adi_fpga9001_hal_customer.h" /* Logging interface */ int32_t(*adi_hal_LogWrite)(void *devHalCfg, uint32_t logLevel, const char *comment, va_list args) = customer_LogWrite; /* Timer interface */ int32_t(*adi_hal_Wait_us)(void *devHalCfg, uint32_t time_us) = customer_TimerWait_us; … Once done, the adi_platform.c code automatically switches to use of the placeholder customer code under the customer\ folder. Following is a code snippet from adi_adrv9001_hal_customer.c, located under customer\adrv9001\.
- Page 40 The issue arises due to a discrepancy between the “standard” bit field control of SPI settings (clock polarity (CPOL), clock phase (CPHA), etc.) and the approach Analog Devices takes with SPI control of the devices. Where most devices use normal Binary encodings for their SPI control (00, 01, 10, 11), Analog Devices uses Gray Code for SPI control (00, 01, 11, 10).
- Page 41 Reference Manual ADRV9001 SOFTWARE INTEGRATION Raspberry Pi HAL Following are some basic examples to fill the functions listed previously for a Raspberry Pi platform. The Broadcom SPI library for the Raspberry Pi handles all configurations and interactions with the ADRV9001. Given that the Raspberry Pi’s connectivity is limited to the GPIO pin headers, individual pins are used for the chip-enable signal and the RESET signal.
- Page 42 Reference Manual ADRV9001 SOFTWARE INTEGRATION delay(1); bcm2835_spi_begin(); bcm2835_spi_transfern(txData, numTxBytes); bcm2835_spi_end(); delay(1); bcm2835_gpio_write(CE_PIN, HIGH); return 0; int32_t customer_adi_adrv9001_hal_spi_read(void *devHalCfg, const uint8_t txData[], uint8_t rxData[], uint32_t numTxRxBytes) /* Customer code goes here */ bcm2835_gpio_write(CE_PIN, LOW); delay(1); bcm2835_spi_begin(); bcm2835_spi_transfernb(txData, rxData, numTxRxBytes); bcm2835_spi_end(); delay(1); bcm2835_gpio_write(CE_PIN, HIGH);...
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Page 43: Developing The Application
Reference Manual ADRV9001 SOFTWARE INTEGRATION Table 12. Logging Level Function Name Purpose ADI_LOGLEVEL_TRACE Logs everything in exhaustive detail. Use only for development. ADI_LOGLEVEL_DEBUG Logs diagnostic information. ADI_LOGLEVEL_INFO Logs state changes in the application. ADI_LOGLEVEL_WARN Logs bad, but recoverable events. ADI_LOGLEVEL_ERROR Logs events that cannot be recovered from. - Page 44 Restrictions Analog Devices maintains the code in the /c_src/devices/* folders. Application developers must not modify this code. Direct SPI read/write operation is forbidden when configuring an ADRV9001 or any other ADI devices used to evaluate the ADRV9001. Developers should only use the high-level API functions defined in the public *.h files.
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Page 45: System Initialization And Shutdown
Reference Manual ADRV9001 SYSTEM INITIALIZATION AND SHUTDOWN There is a graphical user interface (GUI)-based TES to initialize and interact with the ADRV9001 device for evaluation. Through this TES, provide high level system configuration parameters such as signal bandwidth, sample rate, and initial gain control settings to initialize the device. -
Page 46: Api Initialization Sequence
Reference Manual ADRV9001 SYSTEM INITIALIZATION AND SHUTDOWN The TES also generates MATLAB, Python (.py), C# or C code, which includes all high level API initialization calls. Store these automatically generated codes in a location of choice for future use. API INITIALIZATION SEQUENCE As previously mentioned, the initialization sequence consists of a serial of API calls intermixed with user-defined function calls specific to the hardware platform. - Page 47 Reference Manual ADRV9001 SYSTEM INITIALIZATION AND SHUTDOWN Analog Initialization Analog initialization API adi_adrv9001_InitAnalog() is the very first API call to configure the device after all dependent data structures are initialized. It mainly sets the controller bias, enables the reference clock, and validates the profile settings. Resource Loading After analog initialization, a set of APIs is used to load required resources such as stream image, ARM image, programmable FIR (PFIR) coefficients, and so on.
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Page 48: State Change Timing
Reference Manual ADRV9001 SYSTEM INITIALIZATION AND SHUTDOWN Prime and RF Enable The last step in initialization is to move the device from the calibrated to primed state through API call adi_adrv9001_Radio_Channel_Prime() or adi_adrv9001_Radio_Channel_ToPrimed(). The primed state indicates the system is ready for operation when the transmit and receive channels are enabled. - Page 49 Reference Manual ADRV9001 SYSTEM INITIALIZATION AND SHUTDOWN Checks the device clock. ► Checks the RF PLLs. ► A detailed report shows a list of all the tests run, the success or non-success of the tests, and some guidance on the cause of an unsuccessful test.
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Page 50: Warm Boot
Reference Manual ADRV9001 SYSTEM INITIALIZATION AND SHUTDOWN Table 14. APIs for Precalibration and Post-Calibration Checks API Function Description adi_adrv9001_Utilities_SystemDebugPreCalibrate() Function for in-system debugging (precalibration) adi_adrv9001_Utilities_SystemDebugPostCalibrate() Function for in-system debugging (post-calibration) WARM BOOT As described in the Calibrations Initialization section, initial calibration is performed during the initialization of the ADRV9001 device. Depending on the profile configured, initial calibration can take a significant time to complete, especially for complicated profiles such as frequency hopping with dynamic receiver port switching. - Page 51 Reference Manual ADRV9001 SYSTEM INITIALIZATION AND SHUTDOWN Table 15. Warm Boot APIs Description adi_adrv9001_cals_InitCals_WarmBoot_Coefficients_MaxArray_Get() Read the InitCal coefficients needed for warm boot (Non-memory-optimized). adi_adrv9001_cals_InitCals_WarmBoot_Coefficients_MaxArray_Set() Write the InitCal coefficients needed for warm boot (Non-memory-optimized). adi_adrv9001_cals_InitCals_WarmBoot_Coefficients_UniqueArray_Get() Read the InitCal coefficients needed for warm boot and place in allocated memo- ry.
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Page 52: Boot-Up Timing
Reference Manual ADRV9001 SYSTEM INITIALIZATION AND SHUTDOWN Read the vector table data for that cal using adi_adrv9001_Utilities_InitCals_WarmBoot_Coefficients_VectTblChunkRead(). ► Using vector table information, load the warmboot coefficient for that cal using adi_adrv9001_Utilities_InitCals_WarmBoot_Coeffi- ► cients_MaxArrayChunk_Set(). Either load the cal in one chunk or optionally split it into smaller chunks. Call the initial calibration API. - Page 53 Example Results During experiments, Analog Devices focused on characterizing the time taken for the device to boot-up from RESET to RF ENABLED using a given digital mobile radio (DMR) configuration (note: this configuration is just an example use case. It does not represent a “best case”...
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Page 54: Changes To Table 16
Reference Manual ADRV9001 SYSTEM INITIALIZATION AND SHUTDOWN DMR profile ► 1 transmitter ► 1 receiver ► 24 kSPS ► LO = 900 MHz ► Configuration details: ► Low power clock PLL ► Low power receiver ADC ► LVDS SSI ► Processor clock divider = /2 ►... -
Page 55: Changes To Warm Boot Boot-Up Section
ADRV9001 SYSTEM INITIALIZATION AND SHUTDOWN memory can improve with a faster SPI implementation. Also note that the SPI implementation on the Analog Devices platform is not necessarily optimized for speed. So, results for a custom platform can improve. See the Warm Boot section for a method to reduce the boot-up time. -
Page 56: Serial-Peripheral Interface (Spi)
Reference Manual ADRV9001 SERIAL-PERIPHERAL INTERFACE (SPI) The SPI bus provides the mechanism for digital control by a baseband processor. Each SPI register is 8 bits wide, and each register contains control bits, status monitors, or other settings that control all device functions . This section is mainly an information-only section meant to understand the hardware interface used by the baseband processor to control the device. -
Page 57: Spi Broadcast Mode
Reference Manual ADRV9001 SERIAL-PERIPHERAL INTERFACE (SPI) Serial Clock (SCLK) SCLK is the serial interface reference clock driven by the baseband processor (uses the SPI_CLK pin). It is only active while CSB is low. The maximum SCLK frequency is 45.45 MHz. Chip Select Bar (CSB) CSB is the active-low chip select that functions as the bus enable signal driven from the baseband processor to the device (uses the SPI_EN pin). -
Page 58: Spi Data Transfer Protocol
Reference Manual ADRV9001 SERIAL-PERIPHERAL INTERFACE (SPI) Figure 27. SPI Broadcast Mode Block Diagram To enable broadcast mode, users must enable it in the adi_adrv9001_user.h file. The file is located in the ADRV9001 SDK at adrv9001- sdk\pkg\production\c_src\devices\adrv9001\public\include. Table 19. Defines For Broadcast Mode Enablement Define State #define ADI_ADRV9001_PRE_MCS_BROADCAST_DISABLE 1... - Page 59 Reference Manual ADRV9001 SERIAL-PERIPHERAL INTERFACE (SPI) R/Wb - Bit 15 of the instruction word determines whether a read or write data transfer occurs after the instruction byte write. Logic high indicates a read operation; logic zero indicates a write operation. D14:D0 - Bits A<14:0>...
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Page 60: Timing Diagrams
Reference Manual ADRV9001 SERIAL-PERIPHERAL INTERFACE (SPI) Force the CSB line low and keep it low until the last byte is transferred. ► Send the instruction word 0101 0100 0000 000_0 (the last 0 indicates a write operation) to select 0x02A as the starting address. ►... -
Page 61: Spi Test
Reference Manual ADRV9001 SERIAL-PERIPHERAL INTERFACE (SPI) Table 21. SPI Bus Timing Constraint Values Parameter Typical Description 28 ns SCLK period, 3-wire mode 22 ns SCLK period, 4-wire mode 10 ns SCLK pulse width 3 ns CSB setup time to first SCLK rising edge 0 ns Last SCLK falling edge to CSB hold 2 ns... - Page 62 Reference Manual ADRV9001 SERIAL-PERIPHERAL INTERFACE (SPI) Table 22. SPI Main Pin Mapping (Continued) MCS0 MCS1 MCS2 MCS3 MCLK MISO MOSI GPIO3 ✓ GPIO4 ✓ GPIO5 ✓ GPIO6 ✓ GPIO7 ✓ GPIO8 ✓ GPIO9 ✓ GPIO10 ✓ GPIO11 ✓ While multiple pin options exist when assigning a chip-select pin, only a single SPI sub device can be used at a time. Currently, MCS0 can be assigned to any available GPIO pin.
- Page 63 Reference Manual ADRV9001 SERIAL-PERIPHERAL INTERFACE (SPI) Table 23. SPI Main Configure Struct Definition (Continued) Type Name Description adi_adrv9001_spiMasterTriggerSource_e triggerSource SPI master transaction trigger source. uint32_t wakeupTimer_us Monitor mode for early wakeup timer for SPI Main transaction. Only available if trig- gerSource = ADI_ADRV9001_SPI_MASTER_TRIG- GER_SOURCE_MONITOR.
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Page 64: Data Interface
Reference Manual ADRV9001 DATA INTERFACE GENERAL DESCRIPTION This document defines the synchronous-serial interface (SSI), which transfers the data between the ADRV9001 and a baseband processor. The ADRV9001 SSI consists of two receive channels and two transmit channels. The channels are independent and can be configured either as complementary metal oxide semiconductors (CMOS) signals (CSSI) for applications that have narrow RF signal bandwidths and low data-rate, or as low voltage differential signaling (LVDS) signals (LSSI) for applications that require high-speed, low noise, and longer distance data transfer. - Page 65 Reference Manual ADRV9001 DATA INTERFACE Figure 31. ADRV9001 SSI I/Os Mapping Table 25 shows the CMOS SSI electrical specifications. For optimal performance, keep the load capacitance driven by the CMOS outputs to a minimum. The CMOS output drive strength can be increased to compensate for load capacitance larger than 10 pF to increase the edge rate of the output signal during the transition period.
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Page 66: Cmos Synchronous-Serial Interface (Cmos-Ssi)
Reference Manual ADRV9001 DATA INTERFACE Table 25. CSSI Electrical Specification (Continued) Symbol Parameter Units Output-voltage low 0.45 Clock frequency at 80 MHz Load capacitance supported for an 80 MHz clock waveform Table 26. LSSI Electrical Specification Symbol Parameter Conditions Units VDIGIO_1P8 Interface power supply voltage 1.71... - Page 67 Reference Manual ADRV9001 DATA INTERFACE For I data duration and low for Q data duration. For a 16-bit data sample, RX_STROBE is high for 16 clock cycles (I data sample) and low for ► 16 clock cycles (Q data sample). Transmit CSSI The one-lane mode transmits the CSSI of each channel (Tx1 and Tx2).
- Page 68 Reference Manual ADRV9001 DATA INTERFACE Figure 34. Receive CSSI Timing for 2-Bit Symbols (MSB First) Figure 35 shows the transmit CSSI (Tx) for 2-bit data symbols. Figure 35. Transmit CSSI Timing for 2-Bit Symbols (MSB First) Figure 36 shows the receive CSSI (Rx) for 8-bit data symbols. Figure 36.
- Page 69 Reference Manual ADRV9001 DATA INTERFACE Figure 38. Receive CSSI Timing for 16-Bit Symbols (MSB First) Figure 39 shows the transmit CSSI (Tx) for 16-bit data symbols. Figure 39. Transmit CSSI Timing for 16-Bit Symbols (MSB First) Receive CSSI with Two, Four, and Eight Times Data Clock Rates The ADRV9001 receive CSSI supports two, four, or eight times of the data clock rate for some applications.
- Page 70 Reference Manual ADRV9001 DATA INTERFACE Figure 42. Receive CSSI Timing with 8 Times Data Clock Rate for 16-Bit I/Q Data Sample (MSB First), 224 Cycles Figure Figure 44, and Figure 45 show the receive CSSI (Rx1 and Rx2) in the frequency deviation mode with 16-bit data symbol with two, four, and eight times clock rates.
- Page 71 Reference Manual ADRV9001 DATA INTERFACE RX_QDATA3_OUT: output serial data stream of Q sample high byte. ► Figure 46 shows the receive CSSI (Rx1 and Rx2) for a four-lane format with MSB first configuration. Figure 46. Four-Lane Mode Receive CSSI Timing for 16-Bit I/Q Data Sample (MSB First) The four-lane mode CSSI transmits the interface of each channel (Tx1 and Tx2).
- Page 72 Reference Manual ADRV9001 DATA INTERFACE Figure 48. Receive CSSI DDR Clock Relation with Strobe/Data Figure 49 shows the transmit CMOS SSI with DDR clock in relation to the strobe/data, with respect to the ADRV9001. Each edge of the clock (positive and negative) samples the corresponding strobe/data sample based on the interface setup/hold timing. When the baseband processor drives out the transmit SSI clock, strobe, and data to the ADRV9001, the output DDR clock can either be in-phase with the strobe/data or delayed by a quarter cycle of the clock period.
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Page 73: Lvds Synchronous-Serial Interface (Lvds-Ssi)
Reference Manual ADRV9001 DATA INTERFACE Figure 51. Four-Lane Mode Transmit CSSI DDR Timing for 16-Bit I/Q Data Sample LVDS SYNCHRONOUS-SERIAL INTERFACE (LVDS-SSI) Receive LSSI The LSSI receive interface of each channel (Rx1 and Rx2) is an 8-wire LVDS interface consisting of: RX_DCLK_OUT (±): differential output clock. - Page 74 Reference Manual ADRV9001 DATA INTERFACE Figure 53. Receive LSSI Timing for 12-Bit I/Q Data Sample over Two Lanes (MSB First) The RX_STROBE signal is aligned with the first bit of the serialized data (I and Q), and can be configured to be high: For a half-clock cycle at the start of I and Q sample transmit.
- Page 75 Reference Manual ADRV9001 DATA INTERFACE An optional LVDS port (alternative function of Digital GPIO) can also be configured as an output LVDS pad used as a reference clock TX_DCLK_OUT (±) for the baseband processor. Use TX_DCLK_OUT to generate the LSSI clock, strobe, and data signal. Transmit LSSI with Separate Lanes for I and Q Figure 55 shows the transmit LSSI (Tx1 and Tx2) for a 16-bit I/Q data sample with MSB first configuration.
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Page 76: Enhanced Rx Ssi Mode
Reference Manual ADRV9001 DATA INTERFACE Figure 57. Transmit LSSI Timing for 16-Bit I/Q Data Sample Sharing One-Lane Receive LSSI with Two, Four, and Eight Times Data Clock Rates The ADRV9001 receive LSSI supports the two, four, or eight times of the data clock rate for some applications, which is similar with the receiver CSSI mode (see the timing diagrams in the Receive CSSI with Two, Four, and Eight Times Data Clock Rates section). -
Page 77: Power Saving For Lssi
Reference Manual ADRV9001 DATA INTERFACE Figure 58. Enhanced SSI Data Format Some other basic configuration modes, such as MSB/LSB first option, I or Q first option (for CMOS one-lane), and the Long/Short strobe option are similar to the previous SSI LVDS/CMOS 16-bit operations. POWER SAVING FOR LSSI In the time division duplex (TDD) mode, the LVDS SSI pads can be powered down/up dynamically based on the Tx_Enable and Rx_Enable level to save power. -
Page 78: Api Programming
Reference Manual ADRV9001 DATA INTERFACE Table 28. CMOS SSI Timing Specification (Continued) CMOS SSI Timing Description CMOS Tx t Minimum 2 ns Strobe/data setup to clock SETUP CMOS Tx t Minimum 2 ns Strobe/data hold after clock HOLD Table 29. LVDS SSI Timing Specification LVDS SSI Timing Description... - Page 79 Reference Manual ADRV9001 DATA INTERFACE Table 30. SSI Configuration Parameters (Continued) Parameter Type Description Note lvdsRxClkInversionEn bool Set LVDS RX SSI clock inversion enable Default ‘false’ cmosDdrPosClkEn bool Set CMOS DDR positive clock enable Default ‘false’ cmosClkInversionEn bool Set CMOS DDR clock inversion enable Default ‘false’...
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Page 80: Cssi/Lssi Testability And Debug
Reference Manual ADRV9001 DATA INTERFACE Figure 64. RX CMOS DDR SSI Output (cmosDdrPosClkEn=True, cmosClkInversionEn=True) A set of API commands can set and inspect the SSI test/debug functions. Table 31 summarizes these. Table 31. SSI Test/Debug API List SSI Function Name Description adi_adrv9001_Ssi_Rx_TestMode_Configure Configures the SSI test mode for the specified Rx channel. - Page 81 Reference Manual ADRV9001 DATA INTERFACE The ADRV9001 receive SSI can replace the receive channel data with a fixed pattern, ramp, or pseudorandom bit/binary sequence (PRBS) (LSSI only) pattern and send it to the baseband processor. Enable the receive debug function by calling adi_adrv9001_Ssi_Rx_Test- Mode_Configure().
- Page 82 Reference Manual ADRV9001 DATA INTERFACE The ADRV9001 transmit SSI data output can be looped back to receive the SSI data input using API adi_adrv9001_Ssi_Loopback_Set. When the transmit and receive SSI run at the same clock rate, use the pattern generator and checker to verify the functionality of the whole system SSI.
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Page 83: Microprocessor And System Control
Reference Manual ADRV9001 MICROPROCESSOR AND SYSTEM CONTROL The ADRV9001 supports quick configuration from idle states of operation and quick transition between receive and transmit states. Internal blocks called stream processors handle these transitions. The stream processor within the ADRV9001 device performs a series of configuration tasks upon an external request. -
Page 84: System Control
Reference Manual ADRV9001 MICROPROCESSOR AND SYSTEM CONTROL SYSTEM CONTROL Control of the datapaths within the ADRV9001 is done through the API or ENABLE pin controls. For API control, this is reliant on the SPI communication bus and thus, for critical time alignment of powering on/off chains, pin control is recommended for TDD applications. Independently control each datapath with the following enable signals: Table 33. - Page 85 Reference Manual ADRV9001 MICROPROCESSOR AND SYSTEM CONTROL Figure 67. Visualization of Timing Parameters Broadly, the delays in the system are described as follows: Enable Setup Delay is the time taken for the ADRV9001 to power up its analog front end (AFE). This may or may not include PLL tuning ►...
- Page 86 Reference Manual ADRV9001 MICROPROCESSOR AND SYSTEM CONTROL Internal Path Delay is the delay between the SSI port and RF port for either the transmitter or receiver signal chains. It does not include any ► external components, and the ADRV9001 internal calibration algorithm calibrates the internal path delay during the chip initialization stage. As part of the design of a custom setup, use the Internal Path Delay as an approximation, and further measure the entire Propagation Delay of the setup to ensure the accurate transmitter/receiver timing on air in TDD operations.
- Page 87 Reference Manual ADRV9001 MICROPROCESSOR AND SYSTEM CONTROL Table 34. Transmit Timing Parameters Description (Continued) Transmit Timing Parameters Provided by Bounds Comments At typical value: all symbols sent over the interface (including guard symbols) make it onto the air. At maximum bound: no guard symbols are transmitted over the air. enableRiseToAnalogOnDelay User parameter Min: 0 If the transmit propagation delay is long, delay the analog power up for power...
- Page 88 Reference Manual ADRV9001 MICROPROCESSOR AND SYSTEM CONTROL enableRiseToAnalogOnDelay + enableSetupDelay. In such a case, after raising Tx_enable, send some guard data over the interface to ensure all valid transmit data is transmitted on air. Based on the length of the user guard time and transmit timing parameter configurations, only a part or none of the guard data is transmitted to the air. When the frame ends, set enableFallToOffDelay similar to use case 1.
- Page 89 Reference Manual ADRV9001 MICROPROCESSOR AND SYSTEM CONTROL Similar to transmit timing parameters, as shown in Figure 68, receive timing parameters can be categorized into three types: ADRV9001 parameter (ADRV9001 provides to the user), user parameter (user provides to the ADRV9001), and helper parameters (determined by the user, which do not have to provide to the ADRV9001 but can be used to derive other required timing parameters).
- Page 90 Reference Manual ADRV9001 MICROPROCESSOR AND SYSTEM CONTROL Once timing on air is established, raise RX_ENABLE some time before the start of the actual frame. As soon as the receiver analog power up completes, the digital interface turns on. However, if the path has a long propagation delay, the initial data coming off the interface is not the data received over the air.
- Page 91 Reference Manual ADRV9001 MICROPROCESSOR AND SYSTEM CONTROL – t if t is greater than t . For t is less than t , TX_ENABLE rising edge can happen TxEnaRise2On RxEnaFall2Off TxEnaRise2On RxEnaFall2Off TxEnaRise2On − t before TX_ENABLE falling edge. Figure 72 describes both cases.
- Page 92 Reference Manual ADRV9001 MICROPROCESSOR AND SYSTEM CONTROL Hold Time Between RX_ENABLE Rising Edge and RX_ENABLE Falling Edge After a RX_ENABLE rising edge, its falling edge must come after a delay of at least t or t (if controlling LNA power). RxEnaRise2AnaOn RxEnaRise2On To actually receive data, the channel must be on for a duration longer than its propagation delay.
- Page 93 Reference Manual ADRV9001 MICROPROCESSOR AND SYSTEM CONTROL Figure 78. Channel Power-Up and Power-Down Sequence in Different Power Savings Modes (PLL Re-Tune at Frame Boundary Case) In this case, in all power saving modes, the PLL tuning is performed during enableSetupDelay instead of enableRiseToAnalogOnDelay. Therefore, enableSetupDelay is much longer as it must allow time to tune the PLL.
- Page 94 Reference Manual ADRV9001 MICROPROCESSOR AND SYSTEM CONTROL For a specific channel, Power Savings Mode 1 or higher is disallowed when the enableRiseToAnalogOnDelay is less than t ► PowerUpPSM1 API Programming and Default Values for Timing Parameters There is a set of API commands to configure the timing parameters. Because the timing parameters are related to the channel power saving mode, set the channel power saving mode first before configuring the timing parameters.
- Page 95 Reference Manual ADRV9001 MICROPROCESSOR AND SYSTEM CONTROL Figure 79. ADRV9001 Provided Timing Parameters and the System Clock for the Selected Profile in TES Based on the information provided in Figure 79, further configure the ADRV9001 required timing parameters. Default Timing Parameters for Transmit Channels Figure 80 shows the ADRV9001 transmitter's required timing parameters and their minimum, maximum, and default values, and Table 37...
- Page 96 Reference Manual ADRV9001 MICROPROCESSOR AND SYSTEM CONTROL Default Timing Parameters for Receiver Channels Figure 81 shows the ADRV9001 receiver's required timing parameters and their minimum, maximum, and default values. Table 38 summarizes some recommendations. Figure 81. Receiver Timing Parameters Table 38. User Provided Receiver Timing Parameters Timing Parameter Min Value Max Value...
- Page 97 Reference Manual ADRV9001 MICROPROCESSOR AND SYSTEM CONTROL Figure 82. Timing Parameters Configuration in TES Figure 82 shows that only relevant channels are enabled to configure the timing parameters. Enter all the values in ns. The propagation delay is a helper parameter, which is not needed by the ADRV9001. It helps to set the other timing parameters for the ADRV9001. As previously mentioned, use the API command adi_adrv9001_Radio_ChannelEnablementDelays_Configure( ) to set the timing parame- ters.
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Page 98: Api Execution Timing
DGPIO_0~DPGIO_3 is not available for other functions, no matter how many channels are configured in the profile. Analog Devices recommends this debug function to measure the transmitter/receiver ENABLE timing for a given profile, and disable this function to release the DGPIOs usage once measuring is done. -
Page 99: Clock Generation
Reference Manual ADRV9001 CLOCK GENERATION In the ADRV9001, the CLKGEN generates all clocks for the converters and main digital. CLKGEN receives from two clocks, a high performance (HP) clock PLL and low power (LP) clock PLL. The high performance clock PLL has a programmable frequency range of 7.2 GHz to 8.8 GHz. The low power clock PLL can generate a programmable frequency range of 3.3 GHz to 5 GHz. -
Page 100: Arbitrary Sample Rate
Reference Manual ADRV9001 CLOCK GENERATION Table 41. Supported Data Lane Rate by LP CLKPLL (Continued) Standard Serialization Factor Per Data Lane Data Lane Rate 3.84E + 05 FM Direct Modulation 1.54E + 06 TETRA 4.61E + 06 1.15E + 06 2.30E + 06 TETRA 9.22E + 06... - Page 101 Reference Manual ADRV9001 CLOCK GENERATION Table 43. Wideband Dead Zones (Continued) CMOS SDR 1 Lane CMOS SDR 4 Lane CMOS DDR 4 Lane LVDS DDR Lower Upper Bound Bound Custom Custom Custom Custom Dead Zone (MSPS) (MSPS) Custom Extended Custom Extended Custom Extended...
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Page 102: Multichip Synchronization
Reference Manual ADRV9001 MULTICHIP SYNCHRONIZATION INTRODUCTION MCS is needed when an application requires deterministic latency among datapaths within one ADRV9001 device or multiple ADRV9001 devices. For example, in MIMO applications, MCS is the solution to align the data in time for multiple channels. Some applications not only require the delay to be deterministic but also require the phase to be the same. - Page 103 Reference Manual ADRV9001 MULTICHIP SYNCHRONIZATION An external clock module is required to generate the DEV_CLK and MCS pulses for multiple ADRV9001 devices. Each ADRV9001 receives a DEV_CLK and an MCS signal. The MCS signals should arrive at all ADRV9001 devices within one DEV_CLK cycle as they must be sampled by the DEV_CLK, as mentioned in Figure 87.
- Page 104 Reference Manual ADRV9001 MULTICHIP SYNCHRONIZATION To select one of the modes, use this structure: typedef enum adi_adrv9001_McsMode { ADI_ADRV9001_MCSMODE_DISABLED = 0, /*!< Multi Chip Synchronization disabled */ ADI_ADRV9001_MCSMODE_ENABLED, /*!< Multi Chip Synchronization enabled */ ADI_ADRV9001_MCSMODE_ENABLED_WITH_RFPLL_PHASE /*!< Multi Chip Synchronization enabled with RFPLL phase } adi_adrv9001_McsMode_e;...
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Page 105: Mcs Substates (Internal Mcs State Transition)
Reference Manual ADRV9001 MULTICHIP SYNCHRONIZATION To have the phase synchronized, select the MCS and phase sync mode. In this case, consider phase synchronization as additional timing. As frequency hops the PLL phase changes, it takes the additional time to do phase synchronization, as mentioned. This happens at the hop stage, not at the initial stage. -
Page 106: Sample Delay And Read Delay
Reference Manual ADRV9001 MULTICHIP SYNCHRONIZATION and make sure they satisfy the minimum requirement. While MCS is running, the ADRV9001 should be in the MCS transition substate. Table 45 shows the detailed expected states after sending each pulse. Utilize this table to debug any problems that occur during the MCS procedure. Table 45. - Page 107 Reference Manual ADRV9001 MULTICHIP SYNCHRONIZATION Read Delay: It helps delay FIFO read time. Once information is fed in the FIFO, this value guarantees the FIFO has samples for all channels before reading. Figure 91. Tx MCS to Strobe Timing Diagram Figure 92.
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Page 108: Phase Synchronization
The signal uses continuous waves (CW) tones. The reference clock frequency is set to 38.4 MHz. ADI uses the LTE61.44 profile for this test. The test is run from 100 MHz to 3GHz with a 100 MHz step, using internal LOs. Analog Devices also used five different ADRV9001 chips for the test. - Page 109 Reference Manual ADRV9001 MULTICHIP SYNCHRONIZATION Figure 94. Phase Error After Synchronization Between Two LOs analog.com Rev. A | 109 of 377...
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Page 110: Synthesizer Configuration And Lo Operation
Reference Manual ADRV9001 SYNTHESIZER CONFIGURATION AND LO OPERATION The ADRV9001 family devices employ four PLL synthesizers: clock, RF (×2), and auxiliary. Each PLL is based on a fractional-N architecture and consists of a common block made up of a reference clock divider, phase frequency detector, charge pump, loop filter, feedback divider, digital control block, and either a 1 or 4 core voltage-controlled oscillator (VCO). -
Page 111: Added Rf Synthesizer Frequency Accuracy Section
Reference Manual ADRV9001 SYNTHESIZER CONFIGURATION AND LO OPERATION Figure 97. LO Switching Network Figure 98. LO Switching Network (Receiver Channels Configured as Observation Receivers for Transmitter Channels) Note that depending on the application, select the best phase noise or best-power saving options for better optimization.This changes the frequency the internal VCO operates at to optimize for phase noise or power consumption. -
Page 112: Auxiliary Synthesizer
Reference Manual ADRV9001 SYNTHESIZER CONFIGURATION AND LO OPERATION AUXILIARY SYNTHESIZER An integrated auxiliary synthesizer generates the signals necessary to calibrate the device. This synthesizer uses a single core VCO. The reference frequency for the auxiliary synthesizer is scaled from the device clock through the reference clock generation system. The output signal is connected to a switching network and injected into the various circuits to calibrate filter bandwidth corners or into the receive signal chain as an offset LO. - Page 113 Reference Manual ADRV9001 SYNTHESIZER CONFIGURATION AND LO OPERATION When changing the loop filter bandwidth, the typical consideration is the wider the bandwidth, the better the close-in band noise, but the worse the far-out band noise. Trade off between the two to find the optimal setting for the specific application. Note the highest phase frequency detector (PFD) frequency the ADRV9001 supports is 307.2MHz.
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Page 114: Api Operation
Reference Manual ADRV9001 SYNTHESIZER CONFIGURATION AND LO OPERATION Figure 102. Effect of Loop Filter Bandwidth on PLL Phase Noise API OPERATION Data Structure and Enumerations Table 46. Data Structures Related to LO Operation Data Structure Description adi_adrv9001_Device_t Data structure to hold ADRV9001 device instance settings. adi_adrv9001_Carrier_t Carrier structure for carrier configuration. - Page 115 Reference Manual ADRV9001 SYNTHESIZER CONFIGURATION AND LO OPERATION b. If in the PIN mode, do this by moving TX_ENABLE or RX_ENABLE to the low state. 3. Once in the PRIMED state, move the channel state to the calibrated state by calling adi_adrv9001_Radio_Channel_ToCalibrated(). 4.
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Page 116: Frequency Hopping
Reference Manual ADRV9001 FREQUENCY HOPPING Before delving into the frequency hopping feature details, read the Multichip Synchronization Timing Parameters Control sections of this document. In the ADRV9001, FH is mainly designed for TDD applications. It allows to quickly switch radio signals among different frequency channels at different times. -
Page 117: Modes Of Operation
Reference Manual ADRV9001 FREQUENCY HOPPING Figure 104 shows a typical frequency hopping timing diagram with the HOP, Tx Setup, and Rx Setup signals. Besides these, it also shows the hopping frequency selected through a hopping table defined by the BBIC and the timing when hopping frames are on air. The following sections discusses them in more detail. - Page 118 > transition multiplexing) time ADRV9002, ADRV9003, ADRV9004, ADRV9005 support both Fast/Normal calibration modes. ADRV9006 only supports Normal cal mode. Fundamentally, the ADRV9001 defines two modes of PLL usage: PLL Mux and PLL Retune. The PLL Mux mode utilizes two PLLs. While one PLL is in operation, the other one is tuning.
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Page 119: Frequency Hopping Table
Reference Manual ADRV9001 FREQUENCY HOPPING Note in the PLL Mux mode, the rising edge of Tx_Setup or Rx_Setup before a HOP signal edge (the start of hop frame n or end of hop frame n-1) indicates if the hop frame n+1 is operated on Tx or Rx. There is one frame delay in the PLL Mux mode. In another word, to operate Tx on hop frame n+1, the rising edge should appear at hop frame n-1. - Page 120 Reference Manual ADRV9001 FREQUENCY HOPPING Table 49. Hop Table Entry (Continued) Parameter Descriptions rx1GainIndex Starting gain index, if frame is Rx1. rx2GainIndex Starting gain index, if frame is Rx2. Tx1Attenuation_mdB Starting attenuation level, in mdB, if frame is Tx1. Tx2Attenuation_mdB Starting attenuation level, in mdB, if frame is Tx2.
- Page 121 Reference Manual ADRV9001 FREQUENCY HOPPING Index by Pin Rather than automatically incrementing through a hopping table, use DGPIO pins to index any valid entry in the hopping table. Figure 109. DGPIO Table Indexing with PLL Mux Mode At initialization, assign up to 6 DPGIO pins to provide 64 possible indices to the current hopping table. During operation, set the DGPIO pins prior to the upcoming hop edge.
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Page 122: Changes To Example 1: Load New Frequencies With Automatic Ping Pong Section
Reference Manual ADRV9001 FREQUENCY HOPPING In the DGPIO mode, when the hopping table select pin is low, table A is set as the active table, and when the hopping table select pin is set high, table B is set as the active table. The falling or rising edge of HOP Table Select signals the switch to the A or B table, respectively. Figure 110 shows that the HOP Table Select pin is sampled at the hop edge. -
Page 123: Changes To Example 2: Loading A Larger Set Of Frequencies With Manual Table Switch Section
Reference Manual ADRV9001 FREQUENCY HOPPING Figure 111. Load New Frequencies with Automatic Ping Pong with PLL Mux Mode At the first hop signal rising edge, the ADRV9001 reads the hop table entry from table A (the single entry) and prepares that frequency for ►... -
Page 124: Selecting The Channel And Profile
Reference Manual ADRV9001 FREQUENCY HOPPING Load a larger frequency hopping table, which is used in multiple hop frames. Once the table is loaded into the memory, set the Hop Select DGPIO pin, allowing the ADRV9001 to start reading from the second table at the next Hop edge. Ensure the Hop Table Select Pin is set before the appropriate hop edge. -
Page 125: Frequency Hopping Timing
Reference Manual ADRV9001 FREQUENCY HOPPING The ADRV9001 stores the calibration results for the frequency regions. During operation, when it reads the upcoming hopping frequency from the table, it maps it to the appropriate region and applies the corresponding algorithm coefficients. FREQUENCY HOPPING TIMING This section shows the timing information for different FH use cases. - Page 126 Reference Manual ADRV9001 FREQUENCY HOPPING Figure 115. Frequency Hopping Typical Tx Timing for PLL Retune Mode Table 52 summarizes the Tx timing parameters. Table 52. Tx Timing Parameters Delay Parameter Descriptions Bounds Notes Time taken for the ADRV9001 enableSetupDelay No PLL retuning @ hop edge: ~5 µs to power up the analog front PLL retuning @ frame boundary: ~PLL_retune_time txEnaSetup...
- Page 127 Reference Manual ADRV9001 FREQUENCY HOPPING is relative to the hop signal edge after the Rx Setup falling edge. But, for the PLL Retune mode, it is relative to the hop signal edge after the Rx Setup rising edge. Figure 116. Frequency Hopping Typical Rx Timing for PLL Mux Mode Table 53.
- Page 128 Reference Manual ADRV9001 FREQUENCY HOPPING Figure 117. Frequency Hopping Typical TRx Timing for PLL Mux Mode For the TRx operation, because a hop edge can mark both the start and end of an receiver or transmitter frame, the ADRV9001 guarantees that the receiver and transmitter front ends are not powered up at the same time.
- Page 129 Reference Manual ADRV9001 FREQUENCY HOPPING Figure 119. Dual-Hop Timing Figure 119 shows the relationship between Hop 1 and Hop 2 signals in a dual-hop mode of operation. Hop 1 and Hop 2 are triggered independently but must not be triggered at the same time. There must be a minimum of 12 µs offset between Hop 1 and Hop 2 edges. The timing of the channel setup signals is the same as the 'PLL Retune Mode'.
- Page 130 Reference Manual ADRV9001 FREQUENCY HOPPING Table 55. PLL Retune Time (PLL Calibration Mode = Normal) (Continued) PLL Loop BW = 1200 kHz PLL Loop BW = 300 kHz Device Clock (MHz) Average (µs) Std. (µs) Average (µs) Std. (µs) 275.7 55.2 293.5 38.7...
- Page 131 Reference Manual ADRV9001 FREQUENCY HOPPING changed by 10 dB. This FH table was used to easily see the transition between two Tx frames. An ADRV9001 evaluation board and a Tektronix RSA306B spectrum analyzer was used in this measurement. The transition time was measured to be 103.93 µs. From this, the t pllRetune calculated to be 83.93 µs (103.93 µs –...
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Page 132: Additional Frequency Hopping Operations
Reference Manual ADRV9001 FREQUENCY HOPPING Minimum FH Frame Timing As per Table 48 Table 54, the minimum frame timing can be achieved by using: PLL Mux with hop table preprocess mode ► 300 MHz device clock (Max PFD is actually 307.2 MHz which could produce marginally faster retune time) ►... - Page 133 Reference Manual ADRV9001 FREQUENCY HOPPING Figure 125. Rx Only with Long Propagation Delay with PLL Mux Mode Transmitter Only with Long Propagation Delay The ADRV9001 also supports the transmitter only case, where the propagation delay is greater than the duration of a hop frame. To achieve this, specify a parameter as a part of the FH configuration to delay the powering up of the transmitter analog in terms of hop frames.
- Page 134 Reference Manual ADRV9001 FREQUENCY HOPPING Figure 126. Tx Only with Long Propagation Delay for PLL Mux Mode For the PLL Retune mode, the difference is the transmitter setup rising edge, which now marks the beginning of the interface. "txAnalogPower- OnFrameDelay" starts to decrease when the hop signal first samples a High of transmitter setup signal, until it is decreased to 0. When reaching 0, the transmitter analog is powered on as there is no 1 frame delay in the PLL Retune mode.
- Page 135 Reference Manual ADRV9001 FREQUENCY HOPPING Figure 128. Padded Data Method for Tx Only Hopping with Short Propagation Delay Figure 129 shows an alternative to hold off from the transmission until t prior to the analog front end is enabled. Here, the FPGA propagationDelay transmitter DMA involves to delay the transmitting data until the analog front end is ready.
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Page 136: Diversity Mode
Reference Manual ADRV9001 FREQUENCY HOPPING propagation delay of the profile. Table 56 shows the required time to set up and bring down the ORx and Table 57 shows the ORx timing restrictions. Table 56. ORx Timing Parameters Time Required Timing Parameter Time Required (μs) Narrowband Wideband... -
Page 137: Frequency Hopping With Rx/Orx Gain Control
Reference Manual ADRV9001 FREQUENCY HOPPING Figure 131. Diversity Timing Example, Rx1/Rx2 FREQUENCY HOPPING WITH RX/ORX GAIN CONTROL In FH operation, configure the receiver gain control as either manual gain control or automatic gain control (AGC). Configure the AGC as in the non-FH mode and set it to either reset at the start of each Rx frame to a starting gain index, as specified in the hopping table, or to continue from the previous receiver frame. - Page 138 Reference Manual ADRV9001 FREQUENCY HOPPING NCO only. It adds an offset to the current LO frequency. Note that IF operation is supported in the regular Rx FH mode. The IF frequencies are also defined using rx1OffsetFrequencyHz and rx2OffsetFrequencyHz. The difference is that in the regular mode, both the LO and NCO frequencies are changed, while in the NCO-only mode, only the NCO frequencies are changed but LO frequencies are not affected.
- Page 139 Reference Manual ADRV9001 FREQUENCY HOPPING For each channel, the PFIR is switched automatically between the primary and secondary PFIR on each frame of that channel e.g. For Tx1, the primary Tx PFIR is used for the first Tx1 frame and switched to the secondary PFIR for the second Tx1 frame. The PFIRs are switched automatically so no extra control signal is needed.
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Page 140: Integration With Other Advanced Features
Reference Manual ADRV9001 FREQUENCY HOPPING Figure 136. Rx1 PFIR Switching INTEGRATION WITH OTHER ADVANCED FEATURES Frequency Hopping with MCS Frequency Hopping section describes frequency hopping (FH) with multichip synchronization (MCS). Frequency Hopping with DPD Frequency Regions The ADRV9001 supports FH to work with digital predistortion (DPD). The ADRV9001 divides frequencies into 8 frequency regions. Specify the start and end frequencies of 7 regions. -
Page 141: Frequency Hopping Api Programming
Reference Manual ADRV9001 FREQUENCY HOPPING FREQUENCY HOPPING API PROGRAMMING Table 59. Data Structures and Enums Related to Frequency Hopping Data Structure/Enum Description adi_adrv9001_FhHopFrame_t Settings for HOP frame information. adi_adrv9001_FhGainSetupByPinCfg_t Frequency hopping gain setup by pin config. Up to 8 receiver gains and 8 transmitter attenuation levels are loaded to the ARM memory and indexed during frequency hopping operation by up to three GPIO pins. -
Page 142: Transmitter Signal Chain
Reference Manual ADRV9001 TRANSMITTER SIGNAL CHAIN The ADRV9001 device integrates dual direct-conversion (Zero-IF) transmitters. It supports both the time division duplex (TDD) and frequency division duplex (FDD) modes, and is capable of transmitting both narrowband (NB) and wideband (WB) signals. It supports a wide range of applications, such as DMR, P25, and TETRA, as examples of NB standards, and LTE as an example of WB standards. -
Page 143: Digital Front End (Dfe)
Reference Manual ADRV9001 TRANSMITTER SIGNAL CHAIN by two interpolation stages through a flexible combination of interpolation filters. The interpolation ratios and filters are controlled by the profiles. By design, the interpolation images are rejected by more than 110 dB. Between the two interpolation stages, there is an optional FM/FSK modulator called IQ FM/FSK and a digital upconverter (DUC), which can both be bypassed. - Page 144 Reference Manual ADRV9001 TRANSMITTER SIGNAL CHAIN Table 61. Sample Rows from the Tx Gain Table Transmitter Total Transmitter Analog Attenuation Analog Attenuation Digital Attenuation Digital Attenuation Digital Attenuation Attenuation Index Attenuation (dB) Control Word[5:0] (dB) (dB) (Linear) Control Word[11:0] 0.00 0.00 1.00 4095...
- Page 145 Reference Manual ADRV9001 TRANSMITTER SIGNAL CHAIN ADI_ADRV9001_TX_ATTENUATION_CONTROL_MODE_SPI = 1, ADI_ADRV9001_TX_ATTENUATION_CONTROL_MODE_PIN = 3, ADI_ADRV9001_TX_ATTENUATION_CONTROL_MODE_CLGC = 4, } adi_adrv9001_TxAttenuationControlMode_e The following subsections discuss the first three modes. For the CLGC mode, see the Closed Loop Gain Control (CLGC) section. Bypass Mode Select the bypass mode when the transmitter attenuation mode is set as “ADI_ADRV9001_TX_ATTENUATION_CONTROL_MODE_BY- PASS”.
- Page 146 Reference Manual ADRV9001 TRANSMITTER SIGNAL CHAIN GPIO Mode The general purpose input/output (GPIO) mode is another method to control the transmitter attenuation block. In this mode, two GPIO pins are used to increment or decrement the current attenuation value. An API command “adi_adrv9001_Tx_Attenuation_PinControl_Configure()” configures the GPIO pins and sets the step size.
- Page 147 Reference Manual ADRV9001 TRANSMITTER SIGNAL CHAIN Figure 144. Basic Block Diagram of the Slew Rate Limiter Transmitter QEC In the analog circuitry of a direct-conversion transmitter, there are three major non-idealities: gain variation between the I and Q datapath, phase imbalance (non-90 degrees between LO driving I and Q mixers), and differences in the LPF such as group-delay variations. Without properly correcting them, the output spectrum of the transmitter can significantly degrade due to the undesired images.
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Page 148: Analog Front End (Afe)
Reference Manual ADRV9001 TRANSMITTER SIGNAL CHAIN FM/FSK Modulation The ADRV9001 provides a frequency modulation (FM)/frequency shift keying (FSK) for standards that use constant-envelope frequency modulation schemes, such as digital mobile radio (DMR), Analog FM, P25 Phase 1, and Phase 2. It also has the option to perform symbol mapping and interpolation operations on the transmit data received from a baseband processor for FM/FSK modulation. -
Page 149: Transmit Data Chain Api Programming
Reference Manual ADRV9001 TRANSMITTER SIGNAL CHAIN Upconversion Mixer The upconversion mixer translates the baseband signal to RF. It is an IQ modulator, which receives a quadrature baseband and LO signal. Due to the image rejection property of IQ modulators, it produces an output only on one side of the LO, i.e., the image is rejected. The LO leakage and quadrature errors of the mixer are calibrated at initialization, and continually tracked by the transmitter LOL and QEC, as discussed. -
Page 150: Receiver/Observation Receiver Signal Chain
Reference Manual ADRV9001 RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN The ADRV9001 offers dual receive channels. With a minimum number of external components, each receive channel builds a complete RF-to-bits signal chain, which serves as RF front end for a wide range of applications. It supports both the time division duplex (TDD) and frequency division duplex (FDD) modes, and receives both narrowband (NB) and wideband (WB) signals up to 40 MHz. - Page 151 Reference Manual ADRV9001 RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN device. The duplexer is to support both the FDD and TDD modes, which stands for a frequency duplexer in the FDD mode and an RF switch in the TDD mode. Figure 147 shows that each receiver, besides acting as a primary data channel for receiving RF signals, also serves as an observation channel, which receives loopback signals from the transmitter.
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Page 152: Receive Data Chain
Reference Manual ADRV9001 RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN such as the ORx gain. When the ADRV9001 device is in control of the observation channel, it must configure the observation channel properly without any user intervention. Figure 147 shows that each receiver has three inputs. One is the ILB input dedicated for receiving ILB signal. The others are Rx1A/Rx2A and Rx1B/Rx2B inputs. -
Page 153: Analog Front-End Components
Reference Manual ADRV9001 RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN Figure 148. Rx Signal Chain Block Diagram The ADRV9001 supports three standard ADC clocks: ADC-H clock 2211.84 MHz, ADC-M clock 1474.56 MHz, and ADC-L clock 1105.92 MHz for both HP ADC and LP ADC (note that the ADC clock varies with arbitrary sample rate.). In the DFE subsystem, the ADC output signals at three different sample rates go through two decimation stages, as shown in Figure 148, to convert to the desired sample rate by using a flexible... - Page 154 Reference Manual ADRV9001 RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN The fe_gain_cw[7:0] is an 8-bit control word defined in the receiver gain table. Based on the information from the signal detectors, the gain control algorithm finds the index of this gain table so that the corresponding gain control word at this index is used to calculate the gain at the front-end attenuator.
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Page 155: Digital Front End Components
Reference Manual ADRV9001 RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN The LPF is calibrated during device initialization to ensure a consistent frequency corner across all devices. The 3dB bandwidth is set within the device data structure and is profile dependent. The user could optionally tune the 1 dB/3 dB corner frequency of the LPF based on the application. - Page 156 Reference Manual ADRV9001 RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN Figure 151. Decimation Schemes in Receiver Data Chain to Support Various Standards Figure 151 shows that in the NB and WB mode, three different ADC output sample rates are first decimated to a common rate of 184.32 MHz in standard use cases.
- Page 157 Reference Manual ADRV9001 RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN Quadrature Error Correction (QEC) In an ideal analog mixer, the in-phase (I) and quadrature-phase (Q) sinusoidal signals are orthogonal. In addition, the I and Q paths of LPF and ADC should have identical frequency responses. However, in reality, IQ imbalance always exists in the mixer, LPF, and ADC, resulting in quadrature errors.
- Page 158 Reference Manual ADRV9001 RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN /* Linear power is calculated by this formula: linear power = (mantissa * 2^-15) * 2^-exponent */ uint16_t linearPower_mantissa; /* Mantissa of Linear Power */ uint16_t linearPower_exponent; /* Exponent of Linear Power */ } adi_adrv9001_RxRssiStatus_t To accommodate different applications, the ADRV9001 provides some flexibility in configuring the RSSI calculation.
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Page 159: Receive Data Chain Api Programming
Reference Manual ADRV9001 RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN RSSI_dBFS = 3 × (−(exponent) + slicerIn × (18 − 2 × (3 − slicerOffset))) Note, that since this method does not read the slicerIn and slicerOffset registers. It requires that the values for those variables stored in the struct are correct at the time of calculation. - Page 160 Reference Manual ADRV9001 RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN Table 64. A List of Interface Gain APIs (Continued) Receiver Interface Gain API Function Name Description adi_adrv9001_Rx_InterfaceGain_Get Gets the receiver interface gain for the given receiver channel. adi_adrv9001_Rx_DecimatedPower_Get Gets the decimated power at configurable locations for the specified channel. Table 65.
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Page 161: Transmitter/Receiver/Observation Receiver Signal Chain Calibrations
Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS In the ADRV9001, to achieve optimal performance, an ARM performs calibrations, which are classified into two categories: initial calibrations performed at initialization before the device is operational and tracking calibrations performed regularly while the device is operational. Initial calibrations are considered a part of the device initialization, which moves the device from a “STANDBY”... - Page 162 Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS an appropriate level of isolation from the ADRV9001 transmitter output to the antenna to make sure the test tones are not transmitted by the system. Disable the power amplifier during the transmitter initial calibration to achieve this isolation. Initial Calibrations API Programming The ADRV9001 ARM in the device schedules/performs initial calibrations to optimize performance before device operation.
- Page 163 Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS ADI_ADRV9001_INIT_CAL_SYSTEM_ALL = 0x00C00000, } adi_adrv9001_InitCalibrations_e The following enumerator type defines the operating modes for initial calibrations. typedef enum adi_adrv9001_InitCalMode ADI_ADRV9001_INIT_CAL_MODE_ALL, ADI_ADRV9001_INIT_CAL_MODE_SYSTEM_AND_RX, ADI_ADRV9001_INIT_CAL_MODE_LOOPBACK_AND_TX, ADI_ADRV9001_INIT_CAL_MODE_ELB_ONLY }adi_adrv9001_InitCalMode_e; ADI_ADRV9001_INIT_CAL_MODE_ALL runs all the selected initial calibrations, including both receiver (non-loopback and loopback paths) and transmitter initial calibrations.
- Page 164 Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS Table 66. Initial Calibration Mask Bit Assignments (Continued) Bits Corresponding Enum Calibration Description profiles, gain indices and frequency regions, and so on. Perform the calibration only on a single channel. ADI_ADRV9001_INIT_CAL_TX_DAC Tx DAC Initial Calibrates the DAC for the required profile bandwidth.
- Page 165 Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS Table 66. Initial Calibration Mask Bit Assignments (Continued) Bits Corresponding Enum Calibration Description ADI_ADRV9001_INIT_CAL_PLL PLL Initial Performs VCO frequency calibration, VCO real-time temperature/aging Calibration calibration, and charge pump calibration to make RF PLL ready for operation.
- Page 166 Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS Among nine transmitter initial calibrations, except for TX_DAC, all other eight calibrations require to insert the tone/wideband signal into the transmitter datapath from an internal signal generator. Therefore, the internal microprocessor disables the data port to avoid interference. Some calibration algorithms, such as TX_LB_PD, TX_QEC, TX_LOL, TX_DCC, and TX_ATTEN_DELAY further require the use of the observation datapath through ILB to receive the transmitted signal so that a joint analysis is performed by observing the relationship between the transmitted and received signals.
- Page 167 Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS Figure 153. Tx Initial Calibration System Configuration with Signal Generation and Internal Loop Back Figure 153 shows how TX_LB_PD, TX_QEC, TX_LO_LEAKAGE, TX_DCC, and TX_ATTEN_DELAY use the ILB for calibrations. TX_LO_LEAKAGE and TX_QEC calculate the initial correction parameters. TX_LB_PD provides a measurement of the loop back path delay for the TX_LO_LEAKAGE and TX_QEC algorithms.
- Page 168 Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS Figure 154. Transmitter Initial Calibration System Configuration with Signal Generation and External Loopback Type 1 For TX_LO_LEAKAGE, another option is to use ELB2. Figure 155 shows the high level block diagram of system configurations for TX_LO_LEAKAGE initial calibrations using ELB2 (note that the TX_LB_PD initial calibration using ELB2 is required for TX_LO_LEAKAGE).
- Page 169 Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS RX_TIA_CUTOFF, RX_GROUP_DELAY, and RX_QEC_ILB_LO_DELAY, the calibration results are applied in the analog domain for correction. Figure 156 shows the high level block diagram of system configurations for receiver initial calibrations. Note that different calibrations perform at different locations in the receiver datapath, which is simplified in Figure 156.
- Page 170 Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS Figure 157. Tx LO Leakage Performance When LO Change = 100MHz with Full Init Cals, Min Init Cals and No Init Cals Figure 158. Tx Image Rejection Performance When LO Change = 100MHz with Full Init Cals, Min Init Cals and No Init Cals Table 69.
- Page 171 Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS Table 69. Initial Calibration Comparison Summary (Continued) Signal Used by Rerun after LO Calibration External Change User Override Run at (Tones, Wide- Termination Dependent on Which Init Cals >100 MHz Bits Enum Capability Boot band, None)
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Page 172: Tracking Calibrations
Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS initial calibrations to see if the problem is related to some of the enabled calibrations. Similarly, for performance issues during the test, use the optional initial calibrations as a preliminary debug method. Figure 159. - Page 173 Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS ADI_ADRV9001_TRACKING_CAL_TX_LB_PD = 0x00000004, ADI_ADRV9001_TRACKING_CAL_TX_DPD_CLGC = 0x00000010, /* Bit 6-7: Not used (Reserved for future purpose) */ ADI_ADRV9001_TRACKING_CAL_RX_HD2 = 0x00000100, ADI_ADRV9001_TRACKING_CAL_RX_QEC_WBPOLY = 0x00000200, /* Bit 10-11: Not used (Reserved for future purpose) */ ADI_ADRV9001_TRACKING_CAL_ORX_QEC_WBPOLY = 0x00001000, /* Bit 13-18: Not used (Reserved for future purpose) */ ADI_ADRV9001_TRACKING_CAL_RX_BBDC = 0x00080000,...
- Page 174 Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS Table 70. Tracking Calibration Mask Bit Assignments (Continued) Bits Corresponding Enum Calibration Description ADI_ADRV9001_TRACKING_CAL_ORX_QEC_WBPOLY Corrects ORx frequency dependent quadrature error for WB ORx QEC applications. WB Tracking Cali- bration Reserved Reserved Reserved Reserved Reserved Reserved...
- Page 175 Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS Figure 160. Tracking Tx/Rx Calibration Configuration Through TES When an automated TDD configuration is used based on the TDD frame length, some of the tracking calibrations are automatically disabled in TES if the Rx/Tx frame length is less than 1 ms. If the receiver frame is less than 1 ms, RX_HD2, and RX_QEC_WBPOLY are disabled. If the transmitter frame length is less than 1 ms, TX_DPD_CLGC, TX_QEC, and TX_LO_LEAKAGE are disabled.
- Page 176 Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS Figure 161. Tracking Calibration Time Sharing analog.com Rev. A | 176 of 377...
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Page 177: Receiver Gain Control
Reference Manual ADRV9001 RECEIVER GAIN CONTROL The ADRV9001 receivers feature automatic and manual gain control modes for flexible gain control in a wide array of applications. It controls the gain at various stages of the receiver datapath to avoid overloading during the onset of a strong interferer. In addition, it ensures that the receiver digital output data is representative of the root mean square (RMS) power of the receiver input signal so that any internal front-end gain changes to avoid overloading are transparent to the baseband processor. -
Page 178: Receiver Datapath
Reference Manual ADRV9001 RECEIVER GAIN CONTROL The process of compensating for the analog attenuation in the device (prior to the ADC) with a corresponding amount of digital gain before the digital signal is sent to the user. High Threshold Triggers the gain attack event. Some detectors can have multiple high thresholds. Low Threshold Triggers the gain recovery event. - Page 179 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Figure 162. Rx Datapath and Gain Control Blocks In this gain table, each row provides a unique combination of six fields, including front-end attenuator, TIA control, ADC control, external gain control, phase offset, and digital gain/attenuator. Among them, the TIA control that sets the TIA gain, ADC control that sets the ADC gain, and phase offset that compensates for the phase discontinuity during gain change are reserved for future use.
- Page 180 Reference Manual ADRV9001 RECEIVER GAIN CONTROL There are two types of receiver gain tables. One is for gain correction, in which the digital gain is for correcting the small step size inaccuracy in the front-end attenuator. The other one is for gain compensation, which compensates the entire front-end attenuation. The example Table stands for a receiver gain correction table.
- Page 181 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Table 72. New Rx Gain Table Created from the Default Rx Gain Correction Table (Continued) Total Effective Total Effective Gain Table ADRV9002 Attenuation External Attenuation Front-End Attenuator External Gain Phase Digital Gain/Attenuator Index (dB) (dB) Control Word [7:0] Control...
- Page 182 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Measuring External Gain Control Path Delay To accurately apply the attenuation for different components in the datapath, the user needs to measure the external path delay associated with the LNA and set the delay through the API command adi_adrv9001_Rx_ExternalLna_DigitalGainDelay_Set(). Properly load Rx gain table, set gain control and LNA configurations.
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Page 183: Gain Control Modes
Reference Manual ADRV9001 RECEIVER GAIN CONTROL Table 74. Sample Rows from a Modified Rx Gain Table Digital Gain/Attenuator Con- trol Word Gain Table Total Effective ADRV9002 Front-End Attenuator External Gain Phase Control Control [10:0] Index Attenuation (dB) Control Word [7:0] Control [1:0] Offset −2... - Page 184 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Table 77. Peak Detector Gain Steps Overrange/Underrange Gain Step apdHighThresh overrange Reduces gain by apdGainStepAttack apdLowThresh underrange Increases gain by apdGainStepRecovery hbHighThresh overrange Reduces gain by hbGainStepAttack hbUnderRangeHighThresh underrange Increases gain by hbGainStepHighRecovery An overrange condition occurs when the high thresholds are exceeded a configurable number of times within a configurable period. An underrange condition occurs when the low thresholds are not exceeded a configurable number of times within the same configurable period.
- Page 185 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Table 79. changeGainIfThreshHigh Settings changeGainIfThreshHigh[1:0] Gain Change Following APD Overrange Gain Change Following HB Overrange After expiry of gainUpdateCounter After expiry of gainUpdateCounter After expiry of gainUpdateCounter Immediately Immediately After expiry of gainUpdateCounter Immediately Immediately Figure 165 shows how AGC reacts when the changeGainIfThreshHigh is set for the APD or HB detector.
- Page 186 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Figure 166. AGC Operation with HB Detector in Fast Recovery Mode It is highly recommended that the apdHighThresh and hbHighThresh are set to an equivalent dBFS value. Likewise, it is highly recommended that the apdLowThresh and the hbUnderRangeHighThresh are set to equivalent values. This equivalence is approximate, as these thresholds have unique threshold settings and are not exactly equal.
- Page 187 Reference Manual ADRV9001 RECEIVER GAIN CONTROL configured to be close to the same value of dBFS, but assuming some small difference between the thresholds, then as soon as apdLowThresh is exceeded, recovery no longer occurs. The reverse is not true. hbUnderRangeHighThresh does not prevent the gain recovery towards the apdLowThresh.
- Page 188 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Figure 168 shows the operation of the AGC when using the power detector. Considering the power detected in isolation from the peak detectors, the AGC does not modify the gain when the signal level is between overRangeLowPowerThresh and underRangeHighPowerThresh. This is the target range for the power measurement.
- Page 189 Reference Manual ADRV9001 RECEIVER GAIN CONTROL With power detection, the gain change can only happen at the expiration of the gain update counter, which is typically set in the order of hundreds of microseconds or milliseconds. However, power detectors are usually more stable and unlikely to cause frequent gain changes. In addition, it can provide tighter control of the signal level by using a set of inner and outer thresholds compared to the peak detector.
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Page 190: Gain Control Detectors
Reference Manual ADRV9001 RECEIVER GAIN CONTROL consecutive DGPIO pins should always be configured as a pair to retrieve two consecutive bitfields (Bit 0 and Bit 1 or Bit 2 and Bit 3 in both modes). The following enum type defines the DGPIO pin selection. typedef enum adi_adrv9001_GpioPinCrumbSel ADI__GPIO_PIN_CRUMB_UNASSIGNED, ADI__GPIO_PIN_CRUMB_01_00,... - Page 191 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Figure 170. Analog Peak Detector Thresholds There are two APD thresholds, as shown in Figure 170. These thresholds are contained in the agcPeak API structure, apdHighThresh, and apdLowThresh, respectively. The thresholds are typically considered relative to the full scale voltage of the ADC, which is 850 mV peak. The mV setting of the APD thresholds is determined using the following equations.
- Page 192 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Half-Band Peak Detector The HB peak detector is located in the digital domain at the output of the HB filtering block. It can, therefore, also be referred to as the decimated data overload detector because it works on decimated data. Like the APD detector, it functions by comparing the signal level to programmable thresholds.
- Page 193 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Each threshold has an associated counter such that an overrange condition is not flagged until the threshold is exceeded this amount of times in a gain update period. Table 85. Counters for HB Overrange and Underrange Conditions HB Threshold Counter hbHighThresh...
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Page 194: Agc Clock And Gain Block Timing
Reference Manual ADRV9001 RECEIVER GAIN CONTROL AGC CLOCK AND GAIN BLOCK TIMING The AGC clock drives the AGC state machine. In the ADRV9001 device, the default AGC clock (to support a set of standard sample rates) is at 184.32 MHz. When an arbitrary sample rate is adopted in the receiver, the AGC clock varies. The AGC state machine contains three states: the gain update counter, followed by slow loop settling (SLS) delay, and 5 AGC clock cycles delay. -
Page 195: Analog Gain Control Api Programming
Reference Manual ADRV9001 RECEIVER GAIN CONTROL Figure 173. Immediate Gain Attack Causing Delayed Gain Recovery To prevent this happening and to maintain a perfectly periodic gain recovery event, the gain attacks are prevented from happening towards the end of the gain update counter state, as shown in Figure 172. - Page 196 Reference Manual ADRV9001 RECEIVER GAIN CONTROL If selecting the MGC mode, as discussed, manually control the gain through API commands or DGPIO pins. In the API command mode, select a gain index in the gain table through the API function adi_ADRV9001_Rx_Gain_Set(). The API function adi_ADRV9001_Rx_Gain_Get() can read back the gain index selected for a channel.
- Page 197 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Figure 175. Member Listing of adi_adrv9001_GainControlCfg_t Data Structure Table 86. adi_adrv9001_GainControlCfg_t Structure Definition Parameter Description Min Value Max Value Default Value peakWaitTime Number of gain control clock cycles to wait before enabling peak detectors after a gain change.
- Page 198 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Table 86. adi_adrv9001_GainControlCfg_t Structure Definition (Continued) Parameter Description Min Value Max Value Default Value count is exceeded on either the APD or HB detector.1: Gain changes occur immediately when initiated by HB. Gain changes initiated by the APD wait for the gain update to expire.2: Gain changes occur immediately when initiated by APD.
- Page 199 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Table 87. adi_adrv9001_PowerDetector_t Structure Definition (Continued) Parameter Description Min Value Max Value Default Value applicable in TDD modes. This parameter sets the duration of this power measurement. A value of 0 causes the power measurement to run until the next gain update counter expiry.
- Page 200 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Table 88. adi_adrv9001_PeakDetector_t Structure Definition (Continued) Parameter Description Min Value Max Value Default Value not occurring. In the power AGC mode, this threshold prevents further gain increases if the lowThreshPreventGainInc bit is set. apdUpperThreshPeakExceededCount Sets number of peaks to detect above apdHighThresh to cause an APD high overrange event.
- Page 201 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Table 88. adi_adrv9001_PeakDetector_t Structure Definition (Continued) Parameter Description Min Value Max Value Default Value as an underrange event and the gain is recovered by hbGainStepHighRecovery. hbGainStepHighRecovery The number of indices the gain index pointer is increased in the event of an HB underrange high threshold underrange event.
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Page 202: Digital Gain Control And Interface Gain (Slicer)
Reference Manual ADRV9001 RECEIVER GAIN CONTROL Table 90. A List of Rx Gain Control APIs Rx Gain API Function Name Description adi_adrv9001_Rx_GainControl_Mode_Set Configures the Rx gain control mode for a specific channel. adi_adrv9001_Rx_GainControl_Mode_Get Retrieves the currently configured Rx gain control mode. adi_adrv9001_Rx_Gain_Get Reads the Rx gain index for the requested Rx channel. - Page 203 Reference Manual ADRV9001 RECEIVER GAIN CONTROL some extra fields, which are 1 bit of slicer gain or AGC gain change indicator and one of the following: zeros, interface gain, or AGC gain index. For more details, see the Data Interface section.
- Page 204 Reference Manual ADRV9001 RECEIVER GAIN CONTROL applied. The interface gain is determined by RSSI. If the power level is too high, the slicer shifts the signal properly before sending it to the data port to avoid saturation. Let us look at a slicer example that considers three different input signal power levels. The power level 1 fits a data length of 16 bit-width. Power level 2 is 0 dB to 6 dB higher than power level 1, which increases the bit-width by 1.
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Page 205: Digital Gain Control And Interface Gain Api Programming
Reference Manual ADRV9001 RECEIVER GAIN CONTROL DIGITAL GAIN CONTROL AND INTERFACE GAIN API PROGRAMMING The API function adi_adrv9001_Rx_InterfaceGain_Configure() configures the interface gain. The configuration structure adrv9001_RxInter- faceGainCtrl_t is defined as the following: typedef struct adi_adrv9001_RxInterfaceGainCtrl adi_adrv9001_RxInterfaceGainUpdateTiming_e updateInstance; /* Time at which receiver interface gain control must be updated. -
Page 206: Usage Recommendations
Reference Manual ADRV9001 RECEIVER GAIN CONTROL Table 91. A List of Rx Interface Gain Control APIs (Continued) Rx Gain API Function Name Description adi_adrv9001_Rx_InterfaceGain_SeedGain_Set Sets the seed for the Rx interface gain. seedGain is applied by the rising edge on associated GPIO. adi_adrv9001_Rx_InterfaceGain_SeedGain_Get Gets the seed for the Rx interface gain. - Page 207 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Figure 179. TES Configuration for Rx Gain Control Mode and Signal Detector Operation Mode After configuring the Gain Control Mode and Detection Mode, further configure the interface gain, signal detection parameters, and manual control parameters under the Gain Control tab in the TES, as shown in Figure 180 Figure 181, and...
- Page 208 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Figure 180. TES Configuration for Rx Interface Gain analog.com Rev. A | 208 of 377...
- Page 209 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Figure 181. TES Configuration for Signal Detection Parameters Figure 182. TES Configuration for Manual Control Mode Parameters After finishing all the configurations, start the receive operations and observe the receiver gain changes. It is recommended to start from the default settings and change the parameters one by one as needed.
- Page 210 Reference Manual ADRV9001 RECEIVER GAIN CONTROL When the receiver gain control is not working as expected, perform the following simple self-debugging. Check if the gain control mode is set as AGC or MGC. ► Check if the MAX and MIN index are set properly. When set improperly, the gain control capability can be significantly impacted. ►...
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Page 211: Receiver Demodulator
Reference Manual ADRV9001 RECEIVER DEMODULATOR RECEIVER NARROWBAND DEMODULATOR SUBSYSTEM The ADRV9001 receiver narrowband demodulator subsystem, denoted by rxnbdem, is the digital baseband back-end partition of the ADRV9001 receiver channel. Note that the narrowband is commonly used in wireless communication systems. If the channel spacing (also known as channel bandwidth) is 1 MHz or less, it is known as a "narrowband system,"... - Page 212 Reference Manual ADRV9001 RECEIVER DEMODULATOR Carrier Frequency Corrector (CFC) The carrier frequency corrector (CFC) in rxnbdem removes the carrier frequency offset. This module can be bypassed. In a communication system, the desired signal is transmitted by the transmitter at RF over the air. As the clock reference at the transmitter and receiver are independent, this can result in the RF carrier frequency offset between the transmitter and the receiver.
- Page 213 Reference Manual ADRV9001 RECEIVER DEMODULATOR The receiver programmable FIR supports up to 128 taps. Each tap is 24 bits in width with the signed bit included. Four sets of customized FIR profiles can be stored at the initialization phase. One of the four stored FIR profiles can be switched to load on the fly under the control of the BBIC.
- Page 214 Reference Manual ADRV9001 RECEIVER DEMODULATOR j2πf t n A × e , n = 0, 1, 2, . . . (10) where: A is the signal magnitude. is the tone frequency. is the sampling frequency. The output of the frequency discriminator (FD) is D × 2f while the output Mag2 is A Narrowband Programmable FIR The narrowband programmable FIR in rxnbdem performs the pulse shaping filtering or low-pass filtering at the output of the frequency...
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Page 215: Normal Iq Output Mode
Reference Manual ADRV9001 RECEIVER DEMODULATOR Figure 189. Maximum Magnitude/Phase Error of the Resampler Note: The current ADRV9001 software release does not support the resampler configuration. Round Module The round module in rxnbdem maps the ADRV9001 internal data path bit-width to the receiver SSI output. This module can be bypassed if the IQ-22bit mode is chosen. -
Page 216: Application Programming Interface (Api) Programming
Reference Manual ADRV9001 RECEIVER DEMODULATOR hardware block. Cooperating with other hardware blocks, such as the CFC/DDC, programmable FIR filters, and so on, the ADRV9001 receiver narrowband demodulator can perform frequency-shift key (FSK) and FM demodulation under the control of the BBIC. Figure 191. - Page 217 Reference Manual ADRV9001 RECEIVER DEMODULATOR Receiver Programmable FIR (PFIR) Filter API Programming Profile predefined receiver PFIR coefficients or customized receiver PFIR coefficients are automatically loaded during chip initialization. Therefore, there is no need for a baseband processor to call any PFIR coefficients loading API function. The configuration structure adi_adrv9001_PfirWbNbBuffer_t is defined as the following for the PFIR filter coefficients.
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Page 218: Power Saving And Monitor Mode
Reference Manual ADRV9001 POWER SAVING AND MONITOR MODE The ADRV9001 is a high-performance integrated transceiver with low power considerations. To accommodate different user cases, the ADRV9001 provides flexibility for users can flexibly trade-off between power consumption and performance with some of the following static configuration options: Clock phase-locked loop (PLL) option of high performance and low power ►... -
Page 219: Power-Down/Up Channel In Calibrated State
Reference Manual ADRV9001 POWER SAVING AND MONITOR MODE Table 93. Power-Down Modes and Related Power-Down Components (Continued) Power-Down Modes 0 (Default) ARM (+ memories) Approximate Power-Up Time (μs) DEV_CLK = 30Mhz 3200 DEV_CLK = 50Mhz DEV_CLK = 100Mhz DEV_CLK = 30Mhz Approximate Power-Up Time (μs) DEV_CLK = 50Mhz DEV_CLK = 100Mhz... - Page 220 Reference Manual ADRV9001 POWER SAVING AND MONITOR MODE There are two power-saving choices that can be applied for various TDD interframe scenarios: channel power saving (CPS) and system power saving (SPS). Configure either or both options according to the system specifications. Channel Power Saving (CPS) Channel power saving saves power-on channel granularity for dynamic TDD interframe operations.
- Page 221 Reference Manual ADRV9001 POWER SAVING AND MONITOR MODE The API command adi_adrv9001_powerSavingAndMonitorMode_ChannelPowerSaving_Configure() configures the channel power-saving modes for a specified channel. Call it in the calibrated, primed, or RF-enabled state. The new setting cannot take effect immediately after mailbox acknowledgment but at the start of the power-down pin edge (enable falling edge and DGPIO rising edge). Therefore, the baseband processor should allow enough time to send this command and receive or acknowledge it before the next power-down event.
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Page 222: Monitor Mode
Reference Manual ADRV9001 POWER SAVING AND MONITOR MODE ADI_ADRV9001_POWERSAVINGANDMONITORMODE_SYSTEM_MODE_LDO = 4, /*!< LDO power down */ ADI_ADRV9001_POWERSAVINGANDMONITORMODE_SYSTEM_MODE_ARM = 5 /*!< ARM power down */ } adi_adrv9001_PowerSavingAndMonitorMode_SystemPowerDownMode_e; MONITOR MODE Monitor mode is an enhanced sleep mode which includes automatic wake-up on signal detection. Monitor mode allows for autonomous detection of carrier signals in power saving mode. - Page 223 Reference Manual ADRV9001 POWER SAVING AND MONITOR MODE into the monitor mode. The ADRV9001 triggers the wake-up pin to wake up a baseband processor once the carrier is detected in any detection cycle. Figure 197. Monitor Mode: Baseband Processor in Sleep and ADRV9001 in Alternate Sleep and Carrier Detection The monitor mode uses the same power-down modes as System Power Saving (SPS) and they can use the same DGPIO as the power saving trigger interface.
- Page 224 Reference Manual ADRV9001 POWER SAVING AND MONITOR MODE A “DETECTED” state is asserted once the input signal level is beyond the threshold in the “DETECTING” state, and then the following “Wake Up” procedure is started. For example, if the threshold is set to −50 dBFS, when a signal strength higher than this threshold is detected then it is moved to the “DETECTED”...
- Page 225 Reference Manual ADRV9001 POWER SAVING AND MONITOR MODE enables all the buffer data to be retrieved by the user, so no information is lost. To use this mode, it is required to use a higher clock rate as described in the Receive CSSI with Two, Four, and Eight Times Data Clock Rates section.
- Page 226 Reference Manual ADRV9001 POWER SAVING AND MONITOR MODE Figure 199. Monitor Mode with Frequency Hopping Timing Diagram Figure 199, the monitor mode with frequency hopping diagram is given. The monitor mode pin is enabled to start the process and is only disabled when a signal is detected.
- Page 227 Reference Manual ADRV9001 POWER SAVING AND MONITOR MODE Figure 201. Monitor Mode TES GUI (Power Savings and Monitor Mode) In this section, the following settings are available: Initial battery saver delay—the first detection time ► Detection time—all subsequent detection times ►...
- Page 228 Reference Manual ADRV9001 POWER SAVING AND MONITOR MODE Figure 203. Sync Detect Settings 2 3. In the Receive tab, set the interface gain to 0 dB. Figure 204. Sync Detect Settings 3 4. Either run the SYNC path delay or give a known value. Figure 205.
- Page 229 Reference Manual ADRV9001 POWER SAVING AND MONITOR MODE Figure 207. Enable External PLL with SPI Main Settings 1 3. Upload the SPI data needed to wake the external PLL. 4. Select the ‘Enable External PLL’ option. Figure 208. Enable External PLL with SPI Main Settings 2 analog.com Rev.
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Page 230: Digital Predistortion (Dpd)
Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) BACKGROUND One main criteria of a power amplifier (PA) operation is its ability to maintain linearity, i.e., the gain is constant regardless of the input amplitude. However, in practice, a PA can only maintain linearity up to a specific input level, beyond which the gain starts to lower, and the PA enters into a nonlinear or compression region, as shown in Figure 209. -
Page 231: Adrv9001 Dpd Supported Waveforms
Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) In the ADRV9001 device, DPD is considered one of the transmitter tracking calibrations. It is a real-time signal processing with iterative updates to account for hardware variations such as temperature and power level changes. Similar to other transmitter tracking calibrations, it requires a loopback path from the transmitter to the observation receiver (ORx) to perform the calibration. -
Page 232: Dpd With Frequency Hopping (Fh)
Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) Table 95 shows the supported wideband LTE standards and their associated operation parameters. Table 95. Supported Wideband Standards and Associated Operational Parameters LTE Bandwidth (MHz) Number of Carriers PAR (dB) Before CFR Multicarrier Multicarrier Multicarrier Multicarrier Multicarrier... -
Page 233: Closed Loop Gain Control (Clgc)
Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) Figure 213. Raw Transmit Signal Input vs. Linearized Power Amplifier Output Figure 214 shows an example of the ACPR performance before and after DPD. The blue curve represents the ACPR performance before DPD, which shows spectral regrowth. The black curve represents the ACPR performance after DPD. The ACPR performance significantly improves. Figure 214. -
Page 234: Dpd/Clgc Configuration
Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) achieved, the gain in the compression region is adjusted (increased) to match the gain of the lower linear region so that the overall gain is independent of the input or output average power level. This has the advantage of having CLGC focusing on compensating only the PA gain variation mainly due to temperature change. - Page 235 Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) Configure this set of DPD/CLGC parameters before initial calibration. It is defined by the following API data structure. typedef struct adi_adrv9001_DpdInitCfg bool enable; adi_adrv9001_DpdAmplifier_e amplifierType; adi_adrv9001_DpdLutSize_e lutSize; adi_adrv9001_DpdModel_e model; bool changeModelTapOrders; uint32_t modelOrdersForEachTap[4]; uint8_t preLutScale; uint8_t clgcEnable;...
- Page 236 Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) enable, clgcEnable The “enable” parameter places the “DPD Actuator” on the datapath of the specified channel to prepare for DPD operation. The “clgcEnable” parameter enables the CLGC functionality. Do this through TES under the “Advanced Features” tab, as shown in Figure 215.
- Page 237 Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) Figure 217. TES Configuration for External Loopback with External Power Amplifier amplifierType Currently, set the PA type to ADI_ADRV9001_DPD_AMPLIFIER_DEFAULT if DPD is enabled. The default PA type refers to both the MOS and GaN types of PA. lutSize Currently, the supported LUT sizes are 256 and 512.
- Page 238 Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) Figure 218. ADRV9001 DPD Model 4 LUT Configuration Figure 218 shows that d(t) is the raw complex transmit signal before predistortion. Its amplitude is the basis used by the DPD actuator to predistort the d(t) through its LUT. The LUT consists of four taps calculated with precomputed DPD coefficients α, as shown here: |d(t)| + a |d(t)| |d(t)|...
- Page 239 Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) Configure the changeModelTapOrders and modelOrdersForEachTap through TES, as shown in Figure 219 Figure 220. Figure 219 shows the default model tap configuration and d n − l Figure 220 shows a customized model tap configuration, which is equivalent to B[0] = 0x07, B[1] = 0x7F, B[2] = 0x07 and B[3] = 0x06.
- Page 240 Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) bool immediateLutSwitching; bool useSpecialFrame; bool resetLuts; uint32_t timeFilterCoefficient; uint32_t dpdSamplingRate_Hz; uint8_t clgcLoopOpen; int32_t clgcGainTarget_HundredthdB; uint32_t clgcFilterAlpha; int32_t clgcLastGain_HundredthdB; int32_t clgcFilteredGain_HundredthdB; uint32_t captureDelay_us; } adi_adrv9001_DpdCfg_t Table 99 briefly summarizes all the DPD/CLGC post initial calibration parameters described in the data structure. Table 99.
- Page 241 Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) Table 99. DPD/CLGC Post Initial Calibration Parameters (Continued) Parameter Type Description Default Note A coefficient of zero means no filtering. dpdSamplingRate_Hz uint32_t Sampling rate in Hz for the DPD Read only. No effect on actuator and capture.
- Page 242 Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) detectionPeakThreshold It detects a valid data capture for the DPD/CLGC operation if a specified number of samples (countsGreaterThanPeakThreshold) is greater than the defined peak threshold. The DPD/CLGC operation needs a good set of large signal samples to properly model the PA compression behavior.
- Page 243 Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) clgcFilterAlpha This parameter stands for the coefficient of a single-pole filter to smooth the gain measurement. The minimum value is 0, which is equivalent to disable this filter by using the instantaneous gain measurement result. The maximum value is 1, and the default value is 0.75. Set the bigger value to achieve smoother gain measurement results.
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Page 244: Board Configuration
Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) Figure 222. Periodic Updates of DPD/CLGC Enablement in TES BOARD CONFIGURATION Besides configuring the DPD/CLGC preinitial and post initial calibration parameters, configure two other parameters related to the board config- uration: externalLoopbackPeakPower and externalLoopbackPathDelay. Provide these to the ADRV9001 before performing initial calibrations. externalLoopbackPeakPower It indicates the peak power of the ORx input signal loop backed from the transmitter output. -
Page 245: Save And Load Dpd Coefficients From Last Transmission
Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) Figure 223. Configuring Board Configuration Related Parameters Through TES SAVE AND LOAD DPD COEFFICIENTS FROM LAST TRANSMISSION The ADRV9001 DPD also allows to save and load DPD coefficients from the last transmission. Therefore, the DPD can either start from scratch (unity coefficients) or a set of known coefficients. -
Page 246: Dpd/Clgc Api Programming
Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) Figure 225. Define Frequency Hop Regions Through TES Note: In this case, disable immediate LUT switching as the LUT switch only happens at the beginning of each hopping frame with the correct LUT for that LO frequency. In addition, the length of each hopping frame should be sufficient to capture a specified number of samples at the DPD sampling rate plus the additional time it takes for the system to set up the DPD tracking calibration. - Page 247 Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) Figure 226. An Example Setup for Testing the Integrated DPD in Narrowband Applications Once the setup is ready, further configure the TES and available external components properly, which includes the following major steps: Select the desired profile. ►...
- Page 248 Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) The side taps: There are two side taps on each side of the main taps. They are memory terms that compensate for frequency-dependent distortion in the frequency domain and time misalignment between the transmit and receive captured data. The side taps have the same number of polynomial terms, and each side tap has about half of the number of polynomial terms of the main tap.
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Page 249: Measuring The Clgc Target Gain
Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) 1: adi_adrv9001_cals_ExternalPathDelay_Calibrate(). Call this API when the channel state is CALIBRATED. It internally calls the following functions (no need to call these two lower level APIs). ExternalPathDelay_Run(), which runs external path delay calibrations. ► ExternalMinusInternalPathDelay_Measure(), which measures and gets the result of the difference in the path delays between the ILB and ►... - Page 250 Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) 9. Use the TES to measure the transmit gain to help determine the gain target. To do this, enable the “CLGC Loop Open” option under the “Digital Pre-Distortion” tab in TES, as shown in Figure 229.
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Page 251: Dynamic Profile Switching (Dps)
Reference Manual ADRV9001 DYNAMIC PROFILE SWITCHING (DPS) OVERVIEW Dynamic Profile Switching (DPS) is a feature supported by the ADRV9001 to switch among several predefined profiles with different signal bandwidths and sampling rates on the fly. With a switching time of about 50 µs, DPS enables a very fast change to a different profile without the need to reinitialize the chip. -
Page 252: Performing Dps On The Fly
Reference Manual ADRV9001 DYNAMIC PROFILE SWITCHING (DPS) Figure 232. Initial Calibration with DPS PERFORMING DPS ON THE FLY After initialization, the ADRV9001 operates on the main profile with the fixed SSI rate, which does not change during the entire profile switching operation. -
Page 253: Dps Api Programming
Reference Manual ADRV9001 DYNAMIC PROFILE SWITCHING (DPS) Figure 233. BBIC and ADRV9001 Interaction to Perform DPS DPS API PROGRAMMING Table 101 summarizes the set of ADRV9001 API commands for DPS. Refer to the API Doxygen document for more details. Table 101. DPS APIs DPD Rx Function Name Description adi_adrv9001_cals_Dynamic_profiles_calibrate... -
Page 254: Dps Operations In Tes
Reference Manual ADRV9001 DYNAMIC PROFILE SWITCHING (DPS) Transmitter/receiver TIA bandwidth and DAC/ADC sample rate cannot change with a profile switch. ► The physical user interface (for example, CMOS vs. LVDS, or interleaved data vs. non-interleaved data) cannot be modified with a profile ►... - Page 255 Reference Manual ADRV9001 DYNAMIC PROFILE SWITCHING (DPS) Figure 235. Performing DPS in TES analog.com Rev. A | 255 of 377...
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Page 256: Power Amplifier Ramp Control
Reference Manual ADRV9001 POWER AMPLIFIER RAMP CONTROL For a normal TDD burst, the instantaneous transmitter power levels are constrained to the mask defined by the corresponding standards. The mask assures that the near-far situation results in co-channel and adjacent channel interference on the alternate or non-transmission slot. The mask also assures that the power level is adequate for acceptable bit error rate (BER) performance. -
Page 257: Power Amplifier Close Loop Ramp Control
Reference Manual ADRV9001 POWER AMPLIFIER RAMP CONTROL Figure 237. ADRV9001 Power Amplifier Open Loop Ramp Control and Timing Use the API adi_adrv9001_Tx_PaRamp_Configure() to configure the necessary parameters for the power amplifier open-loop ramp control. POWER AMPLIFIER CLOSE LOOP RAMP CONTROL The power amplifier close loop ramp control has a current sensor loop through AuxADC, dedicated digital feedback control logic, and the power amplifier bias control through AuxDAC. -
Page 258: General-Purpose Input/Output (Gpio) And Interrupt Configuration
Reference Manual ADRV9001 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) AND INTERRUPT CONFIGURATION The ADRV9001 has a number of software configurable GPIO pins. Using API functions, users can configure the GPIO pins to operate with a variety of control or monitoring functions. The ADRV9001 has two types of GPIO: 16 digital GPIO pins (referenced to VDIGIO_1P8 supply, designated DGPIO_0 through DGPIO_15 ) ►... -
Page 259: Gpio Operation
Reference Manual ADRV9001 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) AND INTERRUPT CONFIGURATION GPIO OPERATION Set each digital GPIO pin to either the input or output mode. The input mode allows the baseband processor to drive pins on the ADRV9001 to execute specific tasks. The output mode allows the ADRV9001 to output various control or status signals to the baseband processor. Note: There can be conflicts regarding GPIO usage when using combinations of certain features. - Page 260 Reference Manual ADRV9001 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) AND INTERRUPT CONFIGURATION Set the transmitter attenuation control mode to “MODE_PIN” by the API function adi_adrv9001_Tx_AttenuationMode_Set(), and select the appropriate GPIOs for each channel by the API function adi_adrv9001_Tx_Attenuation_PinControl_Configure(). The baseband processor can send the pulses to the ADRV9001 through the specific digital GPIO pins to increase or decrease the transmitter attenuation. Pin-Based Receiver Gain Control Receiver Gain Control section provides a complete description of the receiver gain control.
- Page 261 Reference Manual ADRV9001 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) AND INTERRUPT CONFIGURATION Table 103. Summary of Digital GPIO Output Features (Continued) Feature Description GPIO Pins Available for Feature Manual Pin Toggle Manually control the GPIO output level. API functions set the output pin levels and read the input DGPIO_0 through DGPIO_11 pin levels.
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Page 262: Analog Gpio Operation
Reference Manual ADRV9001 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) AND INTERRUPT CONFIGURATION TX2_DCLK_OUT± functionality when it is in the LVDS mode, or use either DGPIO_14 or DGPIO_15 as the Tx1 DCLK out if it is in the CMOS mode. Note: When the Tx DCLK OUT function is disabled, reuse the corresponding DGPIOs (DGPIO12/13 or DGPIO 14/15) only as input functions. ANALOG GPIO OPERATION The analog GPIO pins serve as the control pins for the external control elements, such as a digital step attenuator (DSA), low-noise amplifier (LNA), external local oscillator (LO)/voltage-controlled oscillator (VCO) components, T/R switch of the TDD system, and so on. -
Page 263: Interrupt
Reference Manual ADRV9001 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) AND INTERRUPT CONFIGURATION analog GPIO level, respectively. Use the manual AGPIO level toggle to control the external RF components, like to power up/down the PA, and so on. Auxiliary DAC Output The auxiliary DAC can supply bias voltages, analog control voltages, or other system functionality. See the Auxiliary Converters and Temperature Sensor section for the details. -
Page 264: Auxiliary Converters And Temperature Sensor
Reference Manual ADRV9001 AUXILIARY CONVERTERS AND TEMPERATURE SENSOR The ADRV9001 device features auxiliary data converters, including four 12-bit auxiliary digital-to-analog converters (AuxDAC) and four 10-bit auxiliary analog-to-digital converters (AUXADC). There is an integrated diode-based temperature sensor to read back the approximate die temperature of the device. -
Page 265: Auxiliary Analog-To-Digital Converter (Auxadc)
Reference Manual ADRV9001 AUXILIARY CONVERTERS AND TEMPERATURE SENSOR Figure 241. AuxDAC DAC Code vs. Output Voltage Characterization Table 107. AuxDAC DAC Code and Output Voltage Characterization Data Summary Mean Gain Vout_0 without Mean Gain Gain Error Mean Gain Mean Offset Vlinear_lo code_min Vlinear_hi... -
Page 266: Temperature Sensor
Reference Manual ADRV9001 AUXILIARY CONVERTERS AND TEMPERATURE SENSOR The AuxADC clock rate is set to 30.72 MHz (or close when the ADRV9001 ARM system clock is changed) to get the best ADC performance. No on-chip calibrations are executed for the AuxADC. The ADC accuracy is limited to the accuracy of the supply reference. A simplified procedure is performed to measure and account for the AuxADC gain and offset errors. -
Page 267: Rf Port Interface Information
Single-ended mode port impedance data is not available. However, a rough assessment is possible by taking the differential mode port ► impedance data, and dividing the real and imaginary components by two. Contact Analog Devices Applications Engineering for the impedance data in the Touchstone format. analog.com Rev. A | 267 of 377... - Page 268 Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION Figure 242. ADRV9001 Transmitter Port Series Equivalent Differential Impedance Figure 243. ADRV9001 Receiver A Port Series Equivalent Differential Impedance analog.com Rev. A | 268 of 377...
- Page 269 Advanced Design System (ADS) Setup Using DAC and SEDZ File Analog Devices supplies the port impedance as an *.s1p series equivalent differential Z (impedance) file. This format allows the simple interface to the advanced design system (ADS) using the data access component (DAC). Term1 is the single-ended input or output and Term2 represents the differential input or output RF port on the ADRV9001.
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Page 270: General Receiver Port Interface
Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION For a wideband match application, because of well-controlled input/output impedance characteristics of the ADRV9001 for the entire range of its RX/TX operational frequency band, implement the minimal matching network to control undesirable impedance deviation typically associated with the high side of the frequency range a balun operates. - Page 271 This example uses the receiver port file and laminate file provided by Analog Devices in the design files package. It uses a more detailed ADS setup than mentioned previously.
- Page 272 Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION Figure 251. Differential Receiver Port and Laminate Add traces and components to emulate the matching network being implemented with various ADS trace blocks, like MLINE, or with a simulated S parameter block from the layout Gerber files. A simulation of the board files is more accurate to include different trace lengths or curves.
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Page 273: General Transmitter Bias And Port Interface
Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION For a more detailed breakdown of this example, refer the ADI Engineer Zone forum tutorials page. GENERAL TRANSMITTER BIAS AND PORT INTERFACE This section considers the DC biasing of the ADRV9001 transmitter outputs and how to interface with each transmitter port. The ADRV9001 transmitters operate over a range of frequencies. - Page 274 Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION RF chokes are used to bias the differential transmitter output lines and connect into a transformer. ► RF chokes are used to bias the differential output lines that are AC-coupled into the input of a driver amplifier. ►...
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Page 275: Impedance Matching Network Examples
Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION Figure 259. ADRV9001 RF Transmitter Interface Configuration D Careful planning is required to select a transmitter balun with a set of external DC bias chokes. It is necessary to find the optimum compromise between the physical choke size, choke DC resistance (R ), and the balun low-frequency insertion loss. -
Page 276: Receiver Rf Port Impedance Matching Network
Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION RECEIVER RF PORT IMPEDANCE MATCHING NETWORK RX1A± and RX2A± Impedance Matching Network The ADRV9001 evaluation board uses both the top and bottom layers of the PCB evaluation platform to accommodate two balun footprints. The 0805 footprint accommodates the high-frequency narrowband baluns, while the backside accommodates the larger DB1627 case-style transformer. - Page 277 Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION Table 112. RX1A± and RX2A± Impedance Matching Network (Continued) L/C/R 245 L/C/R 247 L/C/R 219 C232 L/C/R L/C/R L/C/R L/C/R L/C/R 246 L/C/R 248 L/C/R 220 R232 Frequency Balun L/C 217 L/C 218 L/C 221 C216: (GRM03...
- Page 278 Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION Figure 261. RX1B and RX2B Impedance Matching Networks Table 113. RX1B± and RX2B± Impedance Matching Network L/C/R 249 L/C/R 251 L/C/R 227 C233 L/C/R L/C/R L/C/R 250 L/C/R 252 L/C/R 228 R233 Frequency Balun L/C 222 L/C 224...
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Page 279: Measurement Data
Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION Table 113. RX1B± and RX2B± Impedance Matching Network (Continued) L/C/R 249 L/C/R 251 L/C/R 227 C233 L/C/R L/C/R L/C/R 250 L/C/R 252 L/C/R 228 R233 Frequency Balun L/C 222 L/C 224 L/C/R 237 L/C 225 L/C 229 R227/228:... -
Page 280: Network
Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION Figure 262. Return Loss of RX1(2) A Port Figure 263. Return Loss of RX1(2) B Port Figure 264. Insertion Loss – Simulated RX1(2) A Port – Red Curve RX1(2) B Port – Blue Curve TRANSMITTER RF PORT IMPEDANCE MATCHING NETWORK TX1±... - Page 281 Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION The ADRV9001 evaluation board provides two options in providing the DC common-mode bias for the transmitter outputs. For transformers that provide a DC feed pin, use this to bias the transmitter output. For transformers that do not provide a DC feed pin, bias the transmitter outputs to 1.8 V through pull-up inductors.
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Page 282: Measurement Data
Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION Table 114. TX1± and TX2± Impedance Matching Network (Continued) C346/34 C333 L309 C309 L/C/R 312 L339 R367/36 C334 L/C/R L/C/R L/C/R L310 C310 L/C/R 313 C339 C335 Frequency Balun L/C 311 R361 L/C 314 L/C 316 R312/313: (Murata... -
Page 283: Network
Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION Figure 266. Tx1/Tx2 Return Loss Figure 267. Tx1/Tx2 Insertion Loss, Simulated EXTERNAL LO PORT IMPEDANCE MATCHING NETWORK The external LO1 and LO2 PORT are used to inject LO signals with very high spectral purity for internal receivers and transmitters. Implement the RF matching network for these ports on single-ended and differential sides of the balun to reduce insertion loss due to reflections at the desired LO frequency. - Page 284 Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION Table 115. Specifications for ADRV9001 RF EXT LO Differential Input Pins Parameter Note Typical Unit External LO Frequency FEXTLO 12000 RF Channel Frequency FCHANNEL 6000 External LO Power −6 −3 ~ +3 100 Ω matching Signal amplitude depends on FEXTLO frequency.
- Page 285 Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION For example: For FEXTLO = 500 MHz, the FCHANNEL = 500 MHz For FEXTLO = 1000 MHz, the FCHANNEL = 1000 MHz Figure 269. External LO Impedance Matching Network Table 117. EXTLO1± and EXTLO2± Impedance Matching Network C349 R356 L330/332...
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Page 286: Measurement Data
Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION EXTERNAL LO IMPEDANCE MATCH MEASUREMENT DATA External RF Port Impedance Match Measurement Data for 60 MHz to 6 GHz Band Match Return loss is measured on the EXT LO RF ports of evaluation boards and plotted in Figure 270. - Page 287 Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION Table 118. Device Clock Input Interface Modes Description (Continued) Voltage Applied at MODEA Device Clock Input Electrical DEV_CLK_OUT Divider Value Applied to Interface DEV_CLK_IN Signal Note /XTAL (20MHz to 80MHz) with Nominal Gm multi- plier = x2 1.8 V CMOS or XTAL...
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Page 288: Dev_Clk_In Phase Noise Requirements
Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION Figure 275. Device Clock Input Series Equivalent Differential Impedance Implement the device clock input board traces connected to the device clock inputs balls with stripline transmission lines using inner copper layers in the PCB stackup. The frequency of the device clock input signal can go as high as 1 GHz, and the stripline transmission line approach provides better signal integrity of the clock signal, especially at higher frequency, as well as superior shielding of the RF emission of the device clock signal. -
Page 289: (Mcs) Input
Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION Table 119. DEV_CLK_IN Phase Noise Requirements for 1dB System PN Degradation Compared to an Ideal DEVICE CLOCK Narrow PLL Loop Bandwidth (Approximately 50 kHz) (Default, Wide PLL Loop Bandwidth (Approximately 300 kHz) (User Configured, Typically <3 GHz) Typically >3 GHz ) Frequency Offset From... -
Page 290: Recommendations
Reference Manual ADRV9001 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS The ADRV9001 is a highly integrated RF agile transceiver with significant signal conditioning integrated onto one chip. Due to the integration complexity of the ADRV9001 and its high pin count, a carefully printed circuit board (PCB) layout is important to optimize performance. This section provides a checklist of issues to look for and guidelines on how to optimize the PCB to mitigate performance issues. -
Page 291: Fanout And Trace Space Guidelines
Reference Manual ADRV9001 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Table 121. Impedance Table (Continued) Edge- Target Target Coupled Modeled Modeled Im- Structure Coated Impedance Impedance Linewidth Pitch Reference Linewidth Coplaner pedance (Ω) Layer Type Microstrip (Ω) Tolerance (Ω) (mils) (mils) Layers (mils) Space (mils) Edge-Coupled... -
Page 292: Component Placement And Routing Priorities
Reference Manual ADRV9001 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Figure 277. Trace Fan-Out Scheme on ADRV9001 Evaluation Card (PCB Layer TOP and Layer 8 Enabled) COMPONENT PLACEMENT AND ROUTING PRIORITIES The ADRV9001 transceiver requires a few external components to function, and the ones needed require careful placement and routing to optimize performance. - Page 293 Reference Manual ADRV9001 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Figure 278. RF I/O, DEV_CLK, and Data Port Signal Routing Guidelines RF baluns are typically used to interface single-ended signals to the differential receiver and transmitter ports. These baluns and their ► associated matching circuits affect the overall RF performance.
- Page 294 Reference Manual ADRV9001 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS For each RF transmitter output, install a 10 µF capacitor near the balun power-supply pin connected to the VANA1_1P8, VANA2_1P8 ► supplies. If baluns with no DC supply connection are used, supply power to the transmitter outputs using RF chokes. Connect chokes between the VANA1_1P8 and Tx1 output and VANA2_1P8 and Tx2 output, respectively.
- Page 295 Reference Manual ADRV9001 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Figure 281 shows an example of how to place the ferrite beads, reservoir capacitors, and decoupling capacitors. The recommendation is to connect a ferrite bead between a power plane and the ADRV9001 at a distance from the ADRV9001. The ferrite bead supplies a trace with a reservoir capacitor connected to it.
- Page 296 Reference Manual ADRV9001 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Figure 282. ADRV9001 Power-Supply Domains with Connection Guidelines, All Internal LDOs in Use Power-supply optimization, higher risk (use noise sensitive 1.0 V analog) five power domains: ► 1.8 V digital ► 1.8 V analog ►...
- Page 297 Reference Manual ADRV9001 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Figure 283. ADRV9001 Power-Supply Domains with Connection Guidelines, Some Internal LDOs Bypassed, 1.0V Analog Domain Required Place ceramic 4.7 µF bypass capacitors at the VRFVCO2_1P0, VRFVCO1_1P0, VRX2LO_1P0, VRX1LO_1P0, VCLKVCO_1P0, VAUXV- CO_1P0, VCONV_1P0, and VDIG_0P9 pins. Place these capacitors as close as possible to the device with the ground side of the bypass capacitor placed so that ground currents flow away from other power pins and their bypass capacitors, if at all possible.
- Page 298 Reference Manual ADRV9001 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Figure 284. ADRV9001 AuxADC, SPI, Analog GPIO/AuxDAC, MCS±, and Digital GPIO Signal Routing Guidelines RF AND DATA PORT TRANSMISSION LINE LAYOUT RF Line Design Summary The RF line design is a compromise among many variables. Line impedance, line-to-line coupling, and physical size represent the parameters subject to compromise.
- Page 299 Reference Manual ADRV9001 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Figure 285. Receiver Matching Network on ADRV9001 Evaluation Board The circuit in Figure 285 shows the layout topology for the chosen receiver matching network. Note the location and orientation of each component (placement is critical for expected performance). Similarly, the circuit in Figure 286 shows the layout topology used for the transmitter matching network (see the section for circuit details).
- Page 300 Reference Manual ADRV9001 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Figure 286. Transmitter Matching Network on ADRV9001 Evaluation Board Transmitter Bias and Port Interface This section considers the DC biasing of the ADRV9001 transmitter outputs and how to interface to each transmitter port. At full output power, each differential output side draws approximately 100 mA of DC bias current.
- Page 301 Reference Manual ADRV9001 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Figure 287. ADRV9001 DC Bias Configuration for the Transmitter Output Using Wire-Wound Chokes Figure 288. ADRV9001 DC Bias Configuration for the Transmitter Output Using a Center-Tapped Transformer The ADRV9001 evaluation board provides flexibility to configure each transmitter output to work with either a center-tapped transformer (balun) or a set of two closely matched wire-wounded chokes.
- Page 302 Reference Manual ADRV9001 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Figure 289. 1.8V Transmitter Power-Supply Routing on the ADRV9001 Evaluation Board Figure 290 Figure 291 show an example of the balun feed supply designed to achieve the isolation managed in the evaluation board. DC Balun When using a transmitter balun able to conduct DC, use the system shown in Figure...
- Page 303 Reference Manual ADRV9001 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Figure 291. Transmitter Power Supply Using RF Chokes SSI Data Port Trace Routing Recommendations The data port interface transfers I/Q data between the BBIC/FPGA and ADRV9001 transmitter and receiver datapaths. There are two possible modes of operation for the SSI data port: CMOS-SSI mode (single-ended), with clock rate for data transfer up to 80 MHz.
- Page 304 Reference Manual ADRV9001 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Table 122. FMC Pinout Mapping Used by ADRV9001 Evaluation Board Schematic Net Name FMC Connector Mappings FPGA_REF_CLK+ G02-FMC_CLK1_M2C_P FPGA_REF_CLK- G03-FMC_CLK1_M2C_N DEV_CLK_OUT H04-FMC_CLK0_M2C_P SM_FAN_TACH H05-FMC_CLK0_M2C_N RX1_DCLK_OUT+ G06-FMC_LA00_CC_P RX1_DCLK_OUT- G07-FMC_LA00_CC_N RX1_STROBE_OUT+ H07-FMC_LA02_P RX1_STROBE_OUT- H08-FMC_LA02_N RX1_IDATA_OUT+ G09-FMC_LA03_P RX1_IDATA_OUT-...
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Page 305: Isolation Techniques Used On The
Reference Manual ADRV9001 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Table 122. FMC Pinout Mapping Used by ADRV9001 Evaluation Board (Continued) Schematic Net Name FMC Connector Mappings RESET_TRX D18-FMC_LA13_N DEV_MCS_FPGA_IN+ C18-FMC_LA14_P DEV_MCS_FPGA_IN- C19-FMC_LA14_N DGPIO_0 G18-FMC_LA16_P DGPIO_1 G19-FMC_LA16_N DGPIO_2 H20-FMC_LA15_N DGPIO_3 H17-FMC_LA11_N DGPIO_4 D15-FMC_LA09_N DGPIO_5 C15-FMC_LA10_N... - Page 306 Reference Manual ADRV9001 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS that signals can be routed between the openings without disturbing the isolation benefits provided by the array of apertures. A careful designer notices various bends in the routing of differential paths. Develop and tune these routes through iterative electromagnetic simulation to minimize magnetic field coupling between differential paths.
- Page 307 Reference Manual ADRV9001 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Figure 294. Shielding of Rx Launches Space and align the RF I/O baluns to reduce magnetic coupling from the structures in the balun package. Take care to reduce the crosstalk over shared grounds between baluns. Another precaution is to place and orient the SMA connectors to minimize the connector-to-connector coupling between ports.
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Page 308: Power-Supply Recommendations
(as indicated in the user guide) to maintain the performance criteria over all the process and temperature variations. Analog Devices recommends adding at least 15% margin to all supply maximums to ensure proper operation under all conditions. - Page 309 Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS Table 124. Power-Supply Pins and Functions Pin No. Type Pin Name Voltage [V] Description A1, A2, A13, ANALOG VSSA Analog supply voltage (V A14, B2 to B5, B10 to B13, C2, C5, C10, C13, D1 to D6, D9 to D14, E6, E9, F1 to F3, F6 to F9, F12 to F14, G2,...
- Page 310 Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS Table 124. Power-Supply Pins and Functions (Continued) Pin No. Type Pin Name Voltage [V] Description ANALOG VAUXVCO_1P3 1.3 V internal LDO input supply for auxiliary LO VCO and LO generation circuitry. This pin is sensitive to supply noise.
- Page 311 Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS Evaluation Board Power-Supply Overview Figure 295 outlines the power-supply configuration used on the ADRV9001 evaluation board (EVB). This supply architecture follows a conservative approach in the power-supply design. A switch-mode regulator (ADP5056) is used to achieve power efficiency while generating domains that supply the ADRV9001.
- Page 312 Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS Power Domain Filtering C/FB/C/FB cascaded filters followed by high-current FBs further isolate power signals to the ADRV9001 from each other. Figure 296 outlines a filtered approach implemented on an EVB. Figure 296. An Example of Power Domain Filtering Implemented on ADRV9001 EVB (1.3V -> VRFVCO2_1P3) Figure 297 shows a simulation schematic with power-supply filter components used on the EVB power rails in the ADS environment.
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Page 313: Power-Supply Configurations
Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS domain powers multiple power pins, current tends to be distributed over multiple pins, and this helps to minimize I x R voltage drops on the FB components. RF and Clock Synthesizer Supplies The noise performance of the power domain used to power the RF blocks directly affects the overall transceiver phase noise. Power the power domains using separate traces with extra isolation using a low DCR FB such as the Murata BLM18KG121TN1D or similar device. - Page 314 Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS Figure 300 Figure 301 provide recommendations on how to interconnect power supply when not all of the available RF IOs (transmitters and receivers) are used in the end application. Note that to perform Tx1 tracking calibration or DPD on Tx1, the Rx1 datapath must be available to observe the Tx output.
- Page 315 Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS Figure 299. Available Modes for External 1.0V Power Domain and LO Power-Supply Configuration analog.com Rev. A | 315 of 377...
- Page 316 Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS Figure 300. Power-Supply Modes for Different Number of Active Tx RF IOs analog.com Rev. A | 316 of 377...
- Page 317 Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS Figure 301. Power-Supply Modes for Different Number of Active Rx and Tx RF IOs analog.com Rev. A | 317 of 377...
- Page 318 Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS In cases where not all RF IOs or other interface pins are used in the end application, follow Table 125 for recommendations on what to do with unused pins. Table 125. Instructions Explaining How to Handle ADRV9001 Unused Pins Pin No.
- Page 319 Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS Table 125. Instructions Explaining How to Handle ADRV9001 Unused Pins (Continued) Pin No. Type Mnemonic Unused Instructions Input VTX1LO_1P3 Not applicable. G14, H14 Output TX1+, TX1- Do not connect. Input VANA2_1P8 Not applicable. Output VTX2LO_1P0 Connect to VSSA when unused.
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Page 320: External Lo Port Impedance Matching Power Supply Optimization
Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS Table 125. Instructions Explaining How to Handle ADRV9001 Unused Pins (Continued) Pin No. Type Mnemonic Unused Instructions Input TX2_DCLK_IN- Do not connect. N7, N8, P1, P14 Input VSSD Not applicable. Input TX1_DCLK_IN- Do not connect. Input TX1_DCLK_IN+ Do not connect. - Page 321 Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS Figure 302. Merged VCO Supplies Figure 303. Merged SYNTH Supplies analog.com Rev. A | 321 of 377...
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Page 322: Ldo Configurations
Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS Figure 304. Merged LO Supplies Note: is a schematic notation to merge nets with different names. There is no real component here. The rest of the power supplies need their own FB/cap filter network. Implementing and testing this power solution shows no visible signs of RF performance degradation in phase noise or additional spurs, or any other system level issues. - Page 323 Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS Figure 305. Power-Saving LDO Configurations CHOOSING THE LDO CONFIGURATION Before choosing the proper LDO configurations, it is important to understand the power domains used in the system. The LDO configurations vary depending on the use of RF channels, internal/external LO, or if an external VDDA_1P0 is supplied. Take care when setting the LDO modes to avoid any potential incorrect voltages getting supplied to the internal blocks.
- Page 324 Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS Table 128. LDO Constraints Index Constraints Input Pin Output Pin GP_LDO_1 Do not power down or bypass. VANA1_1P3 VANA1_1P0 DEV_CLK_LDO Do not power down or bypass. VANA2_1P3 VANA2_1P0 CONVERTER_LDO Power down only if all ADCs and DACs must be powered down. VCONV_1P3 VCONV_1P0 RX_1_LO_LDO...
- Page 325 Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS Configuration 0 is the default setup of the LDO array in the power management settings function, where all the LDOs are set to normal operation (mode 1) as follows. adi_adrv9001_PowerManagementSettings_t initialize_powerManagementSettings_35 = { .ldoPowerSavingModes = { ADI_ADRV9001_LDO_POWER_SAVING_MODE_1, ADI_ADRV9001_LDO_POWER_SAVING_MODE_1, ADI_ADRV9001_LDO_POWER_SAVING_MODE_1, ADI_ADRV9001_LDO_POWER_SAVING_MODE_1, ADI_ADRV9001_LDO_POWER_SAVING_MODE_1, ADI_ADRV9001_LDO_POWER_SAVING_MODE_1, ADI_ADRV9001_LDO_POWER_SAVING_MODE_1,...
- Page 326 Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS Figure 306. Standard Operating Config 0 and External LO Config and Rx1/Tx1 Power-Supply Config When the external LO configuration and Rx1/Tx1 configuration are super-positioned onto the standard operating configuration, connect the power supplies per Figure 307.
- Page 327 Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS Figure 307. Tx1/Rx1 External LO Power Solution Now that the hardware configuration is known, determine the LDO configuration and set each LDO to the correct mode. Table 130 outlines the mode needed for each LDO to prevent overvoltage failures or other unwanted errors. Table 130.
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Page 328: External Lo Impedance Match Summary
The design specification for the ADRV9001 EVB shows the best performance of the part with little to no degradation from the PCB design. The Analog Devices applications engineering team recommends the circuit board layout and power-supply decoupling covered in this document. -
Page 329: Adrv9001 Evaluation System
*All variants of the ZC706 evaluation kit are suitable to demonstrate the performance of the ADRV9001. Analog Devices does not guarantee that all future versions and derivatives of the ZC706 will work with the ADRV9001 daughter card and ADRV9001 TES to demonstrate analog.com... - Page 330 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM the ADRV9001 performance. However, as of the date of the current release of this user guide, there are no known incompatibilities with any versions and derivatives of the ZC706. For example, the following versions have been successfully used for evaluation purposes: EK-Z7-ZC706-G and EVAL-TPG-ZYNQ3 Figure 308.
- Page 331 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM 1. Connect the ADRV9001 evaluation card and the ZYNQ ZC706 evaluation platform together, as shown in Figure 310. Use the LPC FMC connector (J5). Take care to align the connectors properly. 2. Make sure that all jumpers on the ZYNQ ZC706 evaluation platform as well as the SW11 position (1, 2, 5 = “A” position) match the settings shown in Figure 308.
- Page 332 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 312. Xilinx ZCU102 Evaluation Board with Jumper Settings and Switch Position Configured to Work with ADRV9001 Evaluation Platform Figure 313. SW6 Positions analog.com Rev. A | 332 of 377...
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Page 333: Hardware Operation
Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 314. ADRV9001 Evaluation Card and ZCU102 Evaluation Platform with Connections Required for Testing The steps to set up the evaluation board for testing are as follows: 1. Connect the ADRV9001 evaluation card and the ZCU102 evaluation platform together, as shown in Figure 314. - Page 334 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM 2. The ZYNQ ZC706 evaluation platform uses a Linux operating system. It takes approximately 30 seconds before the system is ready for operation and can accept commands from the PC software. Observe the boot status on the ZYNQ ZC706 evaluation platform GPIO LEDs (L, C, R, O).
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Page 335: Connection For Multichip Synchronization Transceiver Evaluation Software
316). Stay with the default location C:\Program Files (x86)\Analog Devices\ADRV9002 Transceiver Evaluation Software. If this is not possible, install the TES into any other location with write access. Select the shortcut configuration as the last step of the installation process. - Page 336 PC, the default IP address works. If connecting to the platform through a router, then identify and populate the IP address into the TES before connecting. Contact the Analog Devices applications engineering team if the ADRV9001 evaluation system must operate over a remote connection and a different IP address is required for the Xilinx platform.
- Page 337 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 318. Setup Revision Information Configuring the Device and Board The Device Configuration tab has the setup options for the device. In this page, select the following: ► Product ► Supports ADRV9002, ADRV9003, and ADRV9004. ►...
- Page 338 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM TX supports I/Q, I/Q FM/FSK, direct FM/FSK types. ► Frequency Deviation ► This option is available only for the TX FM type setups. ► Enable ORx1 and ORx2 for IQ input. ► Interface Rate allows to select the rate for the interface. Use this to over or under sample from the sample rate. Provide own PFIR to account ►...
- Page 339 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 320. Receiver/Observation Receiver Loopback Diagram Figure 321. Extended Gain Table Example analog.com Rev. A | 339 of 377...
- Page 340 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 322. Board Configuration Tab Clocks The Clocks tab (Figure 323) provides access to the settings that determine the device clock configuration. This page allows to: Set the device clock. ► Set the device clock frequency. ►...
- Page 341 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Carriers The Carriers tab Figure 324 provides access to the settings that determine the device LO configuration. This page allows to: 1. RX1 Port Switching allows to set up port switching depending on the receiver LO frequency. In this section, set the maximum and minimum values to set up the switching for both the receiver channels.
- Page 342 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 325. Carriers Configuration Tab (Frequency Hopping) Figure 326. Carriers Configuration Tab (Frequency Hopping Tables) Radio The Radio tab (Figure 327) configures the channel enablement, and transmitter and receiver characteristics. Select the channel control mode (hardware enable signals or API command). ►...
- Page 343 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Use "Transmit Data Source" to send data from the FPGA or NCO internal signal source. ► Figure 327. Radio Configuration Tab Advanced Features The Advanced Features tab (Figure 328) provides access to the settings that enable a set of advanced features the device supports. This page allows to: Multichip Sync ►...
- Page 344 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM This can enable the stream status to be seen on the GPIOs to measure the rise-to-analog-on time. ► Figure 328. Advanced Features Tab Figure 329. Synchronous Transfer Option in the Transmit Tab Note that the evaluation software has the synchronous transfer option. This option allows to begin the transfer of data (through the FPGA DMA) on both channels (Tx1 and Tx2 or Rx1 and Rx2) at the same point in time.
- Page 345 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 330. Initial Calibrations Receiver and Transmitter Filters The ADRV9001 evaluation software specifies the custom programmable filter for each channel. These filters are up to 128 taps. The custom filter must be in the .csv or .txt file format and the coefficients must be 24-bit signed integers with no carriage returns. The SDK has an example filter .txt file.
- Page 346 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 331. Rx Filters Figure 332. Tx Filters Receiver and Transmitter Overview The Rx Overview (Figure 333) and Tx Overview (Figure 334) tabs provide more details on the ADRV9001's selected mode of operation using the Device Configuration tab (Figure 319).
- Page 347 Transmit the content of the selected file. The TES comes with some example files. Assuming the default TES installation process, the ► example files are located in C:\Program Files (x86)\Analog Devices\ADRV9002 Transceiver Evaluation Software\Example. Transmit a single-tone, two tones, and zeros. Adjust the digital power of the single- or dual-tone signal as well as the frequency offsets.
- Page 348 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM There is a frequency offset correction option to change the frequency on the air without reprogramming the chip. ► Pressing the play symbol moves the ADRV9001 to the transmit state and starts a process where selected data files for the Tx1 and Tx2 are sent to the ADRV9001.
- Page 349 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Change the capture length in number of samples. ► Change the receiver gain level (gain table index). ► Change the receiver interface gain (in four steps). ► Enable/disable the "Baseband DC Rejection" tracking calibration. ►...
- Page 350 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM | I1 | Q1 | I2 | Q2 When the I and Q column option is selected the data is formatted as follows: Channel 1I | Channel 1Q ----------|----------- | Q1 | Q2 | Q3 | Q4 For receiver frequency deviation, only I samples are shown and all Q samples are 0.
- Page 351 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM GPIO Configuration Use this tab to configure the various GPIO pins for multiple functions, such as power savings, attenuation control, gain control, and hop control pins. Set the System Power Savings in this tab to configure the monitor mode saving level to apply to the part. This section also allows to assign the enable pin for the power saving mode.
- Page 352 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Compensation: It is the process of compensating for the analog attenuation in the device (prior to the ADC) with a corresponding amount of ► digital gain before sending the digital signal to the user. Gain compensation uses the digital gain to effectively undo the analog gain so that the recipient signal from the receiver data stays constant.
- Page 353 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 341. Transmitter Front End Once the pins are assigned, go to the Transmit tab and start normal playback. Then adjust the transmitter attenuation level using the up and down arrows, and this adjusts the transmitter attenuation value by the specified step size. Power Savings and Monitor Mode Specify the certain power-saving mode in this tab (Figure...
- Page 354 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 342. Monitor Mode Window Figure 343. Power Savings and Monitor Mode TDD Enablement Delays For more detailed information on TDD enablement delays, see the Timing Parameters Control section. Automated Time Division Duplexing The ADRV9001 supports the automatic time division duplexing (TDD) operation. Send and receive TDD-framed data by configuring this tab (Figure 344).
- Page 355 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 344. Automated TDD Configuration Tab Figure 345. Automated TDD Timing Diagram TDD Parameter Table The table auto populates the TES based on the chosen configuration file. Enable Column ► Enable/disable the receiver/transmitter channel. ►...
- Page 356 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 346. TDD Frame Timing Illustration Table 131. TDD Signals Signal Description These signals are hardwired to the RX/TX ENABLE pins (used as SETUP signals in FH). RX1 Pin TX1 Pin RX2 Pin TX2 Pin Use as the ORX enable signal when routed to the GPIO assigned as ORX control.
- Page 357 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM DMA disabled, Tx_interface enabled: 0s are transmitted. ► DMA enabled, Tx_interface disabled: data in DMA is not transmitted and is lost. ► DMA enabled, Tx_interface enabled: data in DMA is transmitted. ► The following enum defines the Tx1 DMA trigger. typedef enum adi_fpga9001_DmaTrigger ADI_FPGA9001_DMA_TRIGGER_SMA_1 = 0,...
- Page 358 In case of some erroneous operation, the TES is capable of capturing its state with the Log File functionality that captures the steps that lead to error operation. Send the file created using the Log File function back to the Analog Devices support team for further debug.
- Page 359 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Programming the Evaluation System After configuring all tabs, press Program. This starts the programming and initialization of an evaluation hardware. The TES sends a series of API commands executed by a dedicated Linux application that runs on the Xilinx platform. See a progress bar at the bottom of the window. When programming is complete, the system is ready to operate.
- Page 360 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM External Path Delay Measurement (for DPD) Connect the Tx1 output, through the chosen power amplifier, to the Rx1B input with a cable (add an optional step attenuator to the loop). Configure the TES to indicate there is an external path after the power amplifier in the Board Configuration tab. Enable the DPD from the Advanced Features tab.
- Page 361 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 351. Pop-Up Options Docked in TES Radio State Once the board is connected, view/set the radio state under View->Radio State. Certain operations in the GUI can set the radio to certain states. Be aware of the state the radio is operating on and control the GUI accordingly. Also set the radio to a certain state from this window. Figure 352.
- Page 362 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 353. Power / Temperature Monitoring Window Power Savings This option opens a window with radio button options to change the system state for monitor mode. Select the "Monitoring" button to force the state into monitor mode. Similarly select "Detected" to push the state to detected. There are options to toggle monitor mode enable and wake up pins, also options to toggle both channels power saving pins.
- Page 363 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 355. Timing Diagrams Frequency Hopping Frequency hopping displays the frequency hopping wizard window that assists in setting up the frequency hopping tables in a step-by-step format. For more details, see the Frequency Hopping section.
- Page 364 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 356. Frequency Hopping Wizard Use this wizard to set up all the frequency hopping tables, starting with Use Case and Timing Constraints. Select the type of Carrier Frequency Strategy from ping pong to dynamic table loading. This dictates how many tables to initialize and how the frequency information is loaded from the table.
- Page 365 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 357. Interface Gain Seed / Save Log File The Log File button at the top of the GUI shows the logging information of the system. If the PC is connected to the evaluation platform, the log file shows the version numbers for the different components of the system, including the firmware, FPGA, API, and others.
- Page 366 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 359. Auto Generated Code Options Frequency Hopping TES Examples This section shows three examples to use the TES to achieve frequency hopping for the ADRV9001. For details on the frequency hopping operation, see the Frequency Hopping section.
- Page 367 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM 4. Specify the "Hop Pin" . By default, set it to "Pin 01". 5. Specify the "Hop Mode". Different profiles have certain modes enabled/disabled. a. "Mux Preprocess" indicates two LOs in use for frequency hopping, and the tables are preprocessed before hopping. b.
- Page 368 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 362. Frequency Hopping Executed Sequence 9. Click Program. 10. Upon successful programming, go to the Transmit tab and click Play. A window pops up and indicates the frequency hopping is working in the manual mode. a.
- Page 369 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 364. Manual Frequency Hopping Using TES a. The upcoming frame is assigned to the transmitter (first box). b. There should not be any signal coming out of the transmitter. 3. Click Commit Frame-After-Next to Tx and Perform Hop again. Figure 365.
- Page 370 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Receiver Only The Receiver Only steps are the same as Transmitter Only . The only difference is that instead of clicking Play on the Transmit tab, click Play on the Receive tab. Transceiver The transceiver steps are also very similar, except that click Play on both the Transmit and Receive tabs before operating frequency hopping. Note: Upon reset, all frequencies entries must assign back to "Unassigned".
- Page 371 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM 3. The FPGA board toggles the GPIO pins to set the hop table index according to the loaded sequence. Select the GPIO pins used in the "GPIO Pins for Control of Hop Table" section. Figure 369.
- Page 372 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Receiver Only 1. Select the predefined JSON file DMR_24K_RX_ONLY_FH.json. 2. Hop Pin is set automatically. 3. Go to the Receive tab, set the capture length to the longer value. Here, it is set to 65536. 4.
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Page 373: Evaluation System Troubleshooting
An early image is required for all SDK versions previous to 0.13.0. For SDK releases 0.13.0 or later, a new SD card image is required. This is all taken care of with the Analog Devices SD card imaging software. But check if older versions have been used before. The .img files are also now available on the ADRV9001 product page. - Page 374 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM a. Look for FB E803 located on the TOP side of the PCB, next to the mounting hole. There is a possibility that during transit or when in use, the nut used to keep the PCB in place damaged E803. Ensure that E803 is in place with good connection. If E803 gets broken, replace it with BLM41PG600SN1L from Murata or similar.
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Page 375: Printed Circuit Board Layout Additional Resources
ADDITIONAL RESOURCES Along with this user guide, there are several other resources to aid with evaluation and development with ADRV9001: Product pages for access to documentation, SDK, design resources and ordering information: ADRV9002, ADRV9003, ADRV9004, ► ADRV9005, ADRV9006 Technical articles: ►... -
Page 376: Frequently Asked Questions
Complement of 0101 is 1011 ► FREQUENTLY ASKED QUESTIONS Q1: Will there be an evaluation board for the other family members (ADRV9003/ADRV9004/ADRV9005/ADRV9006)? A1: Not necessary as ADRV9002 is the full featured part that customers can use to emulate and use for all the family members with TES software. - Page 377 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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