Analog Devices ADRV9005 Reference Manual page 294

Reference Manual
PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS
For each RF transmitter output, install a 10 µF capacitor near the balun power-supply pin connected to the VANA1_1P8, VANA2_1P8
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supplies. If baluns with no DC supply connection are used, supply power to the transmitter outputs using RF chokes. Connect chokes
between the VANA1_1P8 and Tx1 output and VANA2_1P8 and Tx2 output, respectively. In both cases, the 10 µF capacitor acts as a
reservoir for transmitter supply current. The
configuration in more detail.
Connect the external clock inputs to the DEV_CLK_IN + (E7) and DEV_CLK_IN − (E8) pins using AC-coupling capacitors. Use a 100 Ω
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termination at the input to the device.
Traces are shielded by surrounding ground with vias staggered along the edge of the differential trace pair. This arrangement creates a
shielded channel that protects the reference clock from any interference from other signals. Refer to the ADRV9001 evaluation board layout
for exact details.
The EXT_LO1+ (A12), EXT_LO1- (A11), EXT_LO2+ (A3), EXT_LO2- (A4) pins are internally DC-biased. If an external LO is used, connect it
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through AC-coupling capacitors.
The data port interface is routed at the beginning of the PCB design and with the same priority as RF signals. This is especially important if
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data port runs in the LVDS configuration. Pay attention to provide appropriate isolation between the data port differential pairs.
Signals with Secondary Routing Priority
Power-supply quality has a direct impact on the overall system performance. To achieve optimal performance, follow the recommendations for
power-supply routing. The following recommendations outline how to route different power domains and which supplies to connect to the same
supply but separated by a ferrite bead.
A general recommendation for power-supply routing is to follow the star methodology, in which each power domain is delivered by a separate
trace from the source supply. Make sure that each power trace is surrounded by ground.
on the evaluation card on Layer 3. Each trace is separated from any other signal by ground plane fill and vias. This approach is essential to
provide necessary isolation between power domains.
Figure 280. Layout Example of Power-Supply Connections Routed with Ground Shielding (Layer 3)
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Transmitter Balun DC Supply Options
Figure 279 illustrates the recommended placement for termination resistor near the DEV_CLK_IN pins.
Figure 279. DEV_CLK_IN Signal Routing Recommendations
section describes the transmitter output power supply
Figure 280 shows an example of such traces routed
ADRV9001
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