Analog Devices ADRV9005 Reference Manual page 26

Reference Manual
ADRV9001 EXAMPLE USE CASES
Table 8. Constraints and Limitations in an FDD Type Repeater Application with Baseband Processor Analyzing Traffic Data (Continued)
Functionality Constraints and Limitations
as high as −9 dBc. Therefore, the RF filtering on the receiver and transmitter path must ensure that signals at the LO harmonic frequencies (up to
ninth in some cases) do not affect overall system performance.
DPD The DPD functionality is not available when the ADRV9001 operates in the 2T2R FDD mode.
Calibrations
During the receiver initialization sequence, ensure that there are no signals present at the receiver input (external LNA must be disabled), and
appropriate termination must be present at the LNA output to avoid reflections of the receiver calibration tones. During the transmitter initialization
sequence, ensure the power amplifier is powered down to avoid unwanted emission of the transmitter calibration tones at the antenna.
No transmitter tracking calibrations are available when the ADRV9001 operates in the 2T2R FDD mode.
AGPIOs Analog GPIOs (operating at 1.8 V level) can be used as read or write digital levels of in the end user system. AGPIOs can be used to control the
states of external components or read back digital logic levels from the external components.
DGPIOs Digital GPIOs can be used to perform real-time monitoring of states of internal ADRV9001 blocks. Digital GPIOs operating as inputs control the
receiver gain, transmitter attenuation, AGC operation, and other elements of the ADRV9001 transceiver. Depending on the ADRV9001 operation,
up to 4 GPIOs may be used by the data port interface.
AuxADC AuxADC can be used to monitor analog voltage (for example, a temperature sensor). The maximum AuxADC input voltage must not exceed 0.9 V.
AuxDAC AuxDAC can be used to control the VCXO responsible for generating the ADRV9001 device clock, or control any circuitry that requires analog
control voltage up to 1.8 V.
DEV_CLK_OUT The ADRV9001 provides a divided down version of the DEV_CLK reference clock input signal on the DEV_CLK_OUT output. This output is
intended to provide reference clock signal to the digital components in the overall system. This output can be configured to be active after power
up and before the ADRV9001 configuration stage.
Multichip Sync If there is no need for multichip synchronization, initialize the ADRV9001 using API functions only.
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