Enhanced Rx Ssi Mode; Changes To Enhanced Rx Ssi Mode Section - Analog Devices ADRV9005 Reference Manual

Reference Manual
DATA INTERFACE
Receive LSSI with Two, Four, and Eight Times Data Clock Rates
The ADRV9001 receive LSSI supports the two, four, or eight times of the data clock rate for some applications, which is similar with the receiver
CSSI mode (see the timing diagrams in the

ENHANCED RX SSI MODE

The Rx SSI LVDS two-lane and CMOS one-lane modes have two enhanced modes to support 22-bit and 15-bit data samples in the I/Q mode.
For the 22-bit data samples, the 32bit interface data bus has the following fields:
22 -bit of data sample (I/Q from Rx datapath: unrounded data samples: RxDataPathI/Q[21:0])
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1-bit = 0 (Constant)
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1-bit Gain Change (Slicer or Index Gain Change flag)
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8-bit Gain (Slicer or Index Gain)
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It produces the following Interface data with a 32-bit data format for the CMOS and LVDS SSI:
LVDS 32-bit: 2 lanes (I and Q) of 32-bit each
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LSSI_DATA_I/Q [31:0] = {RxDataPathI/Q[21:0], b0, Gain_Change, Gain [7:0]}
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CMOS 64-bit: 1 Lane (I and Q)
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CSSI_DATA [63:0] = {RxDataPathI[21:0], b0, Gain_Change, Gain[7:0], RxDataPathQ[21:0], b0, Gain_Change, Gain[7:0] }
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Note: in 22-bit mode, a sample contains 32 bits of I and 32 bits of Q data. This requires the Rx interface to have a 2x clock while the Tx remains
at 1x. For example, if in 16-bit mode, Tx/Rx SSI clock runs at 5 MHz, then in 32 bit mode the Tx SSI clock would need to run at 5 MHz and the
Rx SSI clock would need to run at 10 MHz.
For the 15-bit data samples, the 16-bit interface data bus has the following fields:
15-bit of data sample (15-bit I/Q rounded from 22-bit Rx datapath samples)
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1-bit Gain Change (Slicer or Index Gain Change flag)
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It produces the following interface data with 16-bit data format for the CMOS and LVDS SSI:
LVDS 16-bit: 2 lanes (I and Q) of 16-bit each
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LSSI_DATA_I/Q [15:0] = {RxDataPathI/Q rounded[14:0], Gain_Change}
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CMOS 32-bit: 1 Lane (I and Q)
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CSSI_DATA [31:0] = {RxDataPathI rounded[14:0], Gain_Change, RxDataPathQ rounded[14:0], Gain_Change}
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The format of the enhanced SSI data for 15-bit and 22-bit mode is given in
analog.com
Figure 57. Transmit LSSI Timing for 16-Bit I/Q Data Sample Sharing One-Lane
Receive CSSI with Two, Four, and Eight Times Data Clock Rates
Figure 58.
ADRV9001
section).
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