Auxiliary Synthesizer; External Lo; Rf Pll Loop Filter Recommendations; Pll Phase Noise - Analog Devices ADRV9005 Reference Manual

Reference Manual
SYNTHESIZER CONFIGURATION AND LO OPERATION

AUXILIARY SYNTHESIZER

An integrated auxiliary synthesizer generates the signals necessary to calibrate the device. This synthesizer uses a single core VCO. The
reference frequency for the auxiliary synthesizer is scaled from the device clock through the reference clock generation system. The output
signal is connected to a switching network and injected into the various circuits to calibrate filter bandwidth corners or into the receive
signal chain as an offset LO. Calibrations are executed during the initialization sequence at start-up. There should be no signal present at
the receiver/observation receiver input during tone calibration time. Calibrations are fully autonomous. During the calibration, the auxiliary
synthesizer is controlled solely by the internal ARM microprocessor and does not require any user interactions. The auxiliary LO signal is also
available as an LO source for the observation receiver mixers.

EXTERNAL LO

The device is provisioned with two external LO ports. These ports are available as a pair of balls and are configured to be the input for external
LO signals.
The external LO can receive a signal between 60 MHz and 12 GHz through a matched differential impedance of 100 Ω and delivers a
programmable signal between 30 MHz and 6 GHz as the LO for transmitters and receivers in the device. Maintain the amplitude between ±6
dBm. For more information, see the
Single-ended external LO in is also supported. The matched single-ended impedance is 50 Ω. On-chip duty cycle correction circuit can correct
limited range of external LO duty cycle error if it is not 50%.
Enable external LO with the 1× divider for the carrier frequency range from 500 MHz to 1 GHz.
Single-Ended vs. Differential External LO
Note that the ADRV9001 evaluation board only supports differential external LO. However, there is no restriction to use single-ended LO in the
end system. Change clocks.ext1LoType and clocks.ext2LoType from 0 to 1. The following Enum contains this.
enum adi_adrv9001_ExtLoType {
ADI_ADRV9001_EXT_LO_DIFFERENTIAL = 0,
ADI_ADRV9001_EXT_LO_SINGLE_ENDED = 1}
Figure 99 shows the RF LO generation diagram.

RF PLL LOOP FILTER RECOMMENDATIONS

For optimal phase noise and error vector magnitude (EVM) performance, the ADRV9001 firmware has a look-up table of RF PLL loop filter
bandwidth settings. The ADRV9001 automatically selects the best RF PLL loop filter configuration based on the LO frequency, DEV_CLK
frequency, and PLL bandwidth. Alternatively, program own RF PLL loop filter bandwidth by following the instructions in the
Configuration section.

PLL PHASE NOISE

Figure 100 shows the typical PLL phase noise contributors. For low offset frequencies, the reference clock dominates the phase noise, and for
high offset frequencies, the VCO noise dominates the phase noise. Optimize the phase noise by:
Providing better reference clock source.
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Providing higher reference clock frequency (PFD).
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Adjusting the loop filter bandwidth to trade-off between the close-in band and far-out band noise.
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External LO Port Impedance Matching Network
Figure 99. RF LO Generation Diagram
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ADRV9001
Loop Filter
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