Power Amplifier Ramp Control; Power Amplifier Open-Loop Ramp Control - Analog Devices ADRV9005 Reference Manual

Reference Manual

POWER AMPLIFIER RAMP CONTROL

For a normal TDD burst, the instantaneous transmitter power levels are constrained to the mask defined by the corresponding standards. The
mask assures that the near-far situation results in co-channel and adjacent channel interference on the alternate or non-transmission slot. The
mask also assures that the power level is adequate for acceptable bit error rate (BER) performance.
The RF power amplifier is an active device closest to the antenna. There should be precise control for the power amplifier output ramping up
and down to fully comply with the transmitter mask requirements of the TDD standards. Ramp up/down the baseband IQ signals to control the
power amplifier output level, or control the power amplifier power supply and bias voltage directly, to ramp up/down the power amplifier output
level.
The direct power amplifier ramp control needs an independent microcontroller (MCU) through the monitoring channels to sense the power
amplifier status and further generate the control targets based on the given function routine. Therefore, the ADRV9001 has highly integrated
hardware and software functions to achieve the direct power amplifier ramp control function.
The integrated AuxDACs, AuxADCs, and GPIOs in ADRV9001 provide sufficient monitoring and controlling channels.
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A fully digital hardware control loop in the ADRV9001 offers high controlling precision to overcome all sorts of non-ideal facts in the loop.
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The integrated ARM core in the ADRV9001 has the intelligence to protect and control the power amplifier. This intelligence includes
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auto calibration, always-on-time monitoring independent of SPI communication speed, customized self-decision response, and autonomous
recovering.
The ADRV9001 supports open-loop and closed-loop power amplifier ramp controls. Apply either of them based on the system requirements.

POWER AMPLIFIER OPEN-LOOP RAMP CONTROL

Tune the power amplifier bias voltage (Vgs) to control the power amplifier output level. The Vgs range varies with different power amplifier
types. An external amplifying and buffering circuit cooperating with the ADRV9001-integrated AuxDACs is necessary because the ADRV9001
AuxDAC 0.05 V ~ 1.75 V output voltage may not be enough for the power amplifier bias voltage control,
power amplifier open-loop ramp control circuits, where the operational amplifier (OPA) can be AD8542 or ADA4692. This example uses two
AuxDAC channels: one to generate the ramp waveform and another optional one to generate the offset voltage to compensate for the power
amplifier characteristic difference.
Figure 236. Power Amplifier Open Loop Ramp Control with ADRV9001 AuxDAC Output Amplifying and Buffering Circuits
Each transmitter channel of the ADRV9001 has an independent power amplifier ramp control logic, and an independent look-up table (LUT)
storing the DAC codes for the ramp up/down waveform. The maximum depth of the LUT is 256. Flexibly configure the ramp-up and ramp-down
waveforms with this 256 size LUT. Also set the full 256 size LUT for ramp-up and down simultaneously if the transmitter mask has symmetric
up/down behaviors.
Power amplifier ramp enable can be triggered by SPI, TX_ENABLE, or a DGPIO. The TX_ENABLE, or DGPIO mode is recommended for
accurate TDD operation timing.
triggered at the rising edge and falling edge of the power amplifier ramp EN (TX_Enable or DGPIO), respectively, with an optional start delay.
The stored DAC codes in LUT is sent to AuxDAC accordingly. Calculate the ramp up/down duration by the ramp clock period times the relative
LUT length.
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Figure 237 shows the power amplifier open-loop ramp control and timing. Power amplifier ramp up and down is
ADRV9001
Figure 236 shows an example of the
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