Power Saving For Lssi; Ssi Timing Parameters; Added Figure 58 - Analog Devices ADRV9005 Reference Manual

Reference Manual
DATA INTERFACE
Some other basic configuration modes, such as MSB/LSB first option, I or Q first option (for CMOS one-lane), and the Long/Short strobe option
are similar to the previous SSI LVDS/CMOS 16-bit operations.

POWER SAVING FOR LSSI

In the time division duplex (TDD) mode, the LVDS SSI pads can be powered down/up dynamically based on the Tx_Enable and Rx_Enable
level to save power. Three LSSI power-down modes are defined for different requirements
Down_Set is used to set the power-down mode for a specified channel.
Table 27. LSSI Power-Down Mode
LSSI Power-Down Mode
ADI_ADRV9001_SSI_POWER_DOWN_DISABLED
ADI_ADRV9001_SSI_POWER_DOWN_MEDIUM
ADI_ADRV9001_SSI_POWER_DOWN_HIGH

SSI TIMING PARAMETERS

Figure 59 and Figure 60 show the receive SSI and transmit SSI timing
CMOS SSI and LVDS SSI.
Table 28. CMOS SSI Timing Specification
CMOS SSI
CMOS Rx t Maximum
DELAY
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Figure 58. Enhanced SSI Data Format
Description
All SSI PADS are powered up in PRIMED.
RX_DCLK_OUT and TX_DCLK_OUT SSI pads are powered up, TX_DCLK_IN and all Tx/Rx
STROBE and DATA SSI pads are powered down in PRIMED.
All SSI pads are powered down in PRIMED.
diagrams.Table 28
Figure 59. Receive SSI Timing Diagram
Figure 60. Transmit SSI Timing Diagram
Timing Description
4.5 ns Clock to strobe/data delay
ADRV9001
(Table 27). The API adi_adrv9001_Ssi_Power-
and Table 29 show the timing specifications for the
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