Analog Devices ADRV9005 Reference Manual page 10

Reference Manual
PRODUCT HIGHLIGHTS
For sample rates above 2.5 MHz, single channel data is serialized over four lanes with two additional lanes required for a clock (SDR or DDR)
and a frame synchronization signal, which supports a maximum sample rate of 20 MHz.
The LVDS electrical interface supports two modes of operation. The 32 total bits of I and Q data are serialized over one LVDS lane (32 bits
composed of 16 bits of I and 16 bits of Q data) or two LVDS-SSI lanes (each dedicated to 16 bits of I or Q data), with two additional lanes total
required for a DDR clock and a frame synchronization signal. The sample rates ranging from 24 kHz to 61.44 MHz are supported through the
LVDS-SSI interface, resulting in a maximum lane rate of 983.04 MHz.
Note that in the LVDS-SSI mode, 12-bit I and Q words are supported for most sample rates.
RF LO Frequency Range and Multiplexing
The ADRV9002 supports an RF LO range from 30 MHz to 6 GHz. RF LOs can be generated through two internal PLLs or applied externally to
the device.
An LO multiplexing scheme on the
RFPLLs can operate concurrently and independently, off a common reference clock, thus enabling FDD operation, single or dual frequency
repeater operation, multiband TDD operation, and diversity operation among various other configurations.
Frequency Hopping
The ADRV9002 supports various forms of frequency hopping with the main distinguishing factor among them being the frequency transition
time.
There is a fast frequency hopping (FFH) mode to support up to 128 hop frequencies or less, and these are preloaded through two hopping
tables onto the ADRV9002 at power-up. All the frequencies can be cycled through in a circular buffer fashion.
A random access of the hopping frequencies is also supported, whereby a finite set of frequencies already preloaded onto the
be hopped between in a random manner determined by the user. Select the next frequency to hop by asserting a frequency index word onto
the GPIO bus.
In addition, the ADRV9002 also supports the loading of hopping frequencies on the fly. In this mode, change the hopping frequency while
performing hopping.
Profile Switching
The ADRV9002 supports rapid switching among different RF channel profiles. A transmit or receive RF channel profile contains settings
such as bandwidth, sample rate, filtering, input port selection, automatic gain control (AGC) settings, and algorithm configuration. The profile
switching supports switching among a set of waveforms with different sampling rates on the fly.
Low IF Reception
The receiver digital datapath on the
(NCO). The RX LO is offset from the frequency of the desired channel. Then, the digital mixer and NCO are used to down convert the signal to
baseband before being processed by a baseband processor.
There are several advantages to offset the RX LO from the frequency of the desired channel: Impairments in the the RX LO, such as
LO-leakage, can be avoided. The effect of flicker noise from baseband circuits can be reduced as the received signal is offset from the DC in
the analog signal path. Also, image rejection can be improved if the RX LO is offset enough from the required channel, such that the image
frequency lies in the attenuation region of the external RF filter.
The low IF reception mode predominately targets low bandwidth channels, which supports offsets in the range of ± 20 MHz from the receiver
LO.
Receive Dynamic Range and Blocking
As shown in Figure 2, the ADRV9002
programmable digital decimation and filtering datapath follows the ADC. There is RF analog gain control in an analog attenuator, and additional
gain in the digital datapath through AGC loops.
analog.com
ADRV9002 routes either of the RFPLLs to any of the transmit or receive channels. The RF channels and
ADRV9002 contains an optional digital mixer driven by a programmable numerically controlled oscillator
receive path consists of an input mixer followed by a baseband filter that drives an ADC. A highly
ADRV9001
ADRV9002 can
Rev. A | 10 of 377