Analog Devices AD7195 Manual

4.8 khz, ultralow noise, 24-bit sigma-delta adc with pga and ac excitation

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FEATURES

AC or DC sensor excitation

RMS noise: 8.5 nV at 4.7 Hz (gain = 128)

16 noise-free bits at 2.4 kHz (gain = 128)

Up to 22.5 noise-free bits (gain = 1)

Offset drift: 5 nV/°C

Gain drift: 1 ppm/°C

Specified drift over time

2 differential/4 pseudo differential input channels

Automatic channel sequencer

Programmable gain (1 to 128)

Output data rate: 4.7 Hz to 4.8 kHz

Internal or external clock

Simultaneous 50 Hz/60 Hz rejection

Power supply

: 4.75 V to 5.25 V

: 2.7 V to 5.25 V

Current: 6 mA

Temperature range: –40°C to +105°C

Package: 32-lead LFCSP

INTERFACE

3-wire serial

SPI, QSPI™, MICROWIRE™, and DSP compatible

Schmitt trigger on SCLK

APPLICATIONS

Weigh scales

Strain gage transducers

Pressure measurement

Temperature measurement

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

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Sigma-Delta ADC with PGA and AC Excitation

FUNCTIONAL BLOCK DIAGRAM

AGND

AIN1

AIN2

AIN3

AIN4

MUX

AINCOM

BPDSW

AGND

TEMP

SENSOR

AD7195

ACX1

4.8 kHz, Ultralow Noise, 24-Bit

Chromatography

PLC/DCS analog input modules

Data acquisition

Medical and scientific instrumentation

GENERAL DESCRIPTION

The AD7195 is a low noise, complete analog front end for high

precision measurement applications. It contains a low noise,

24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC).

The on-chip low noise gain stage means that signals of small

amplitude can be interfaced directly to the ADC. The AD7195

contains ac excitation, which is used to remove dc-induced

offsets from bridge sensors.

The device can be configured to have two differential inputs or

four pseudo differential inputs. The on-chip channel sequencer

allows several channels to be enabled, and the AD7195 sequentially

converts on each enabled channel. This simplifies communication

with the part. The on-chip 4.92 MHz clock can be used as the

clock source to the ADC or, alternatively, an external clock or

crystal can be used. The output data rate from the part can be

varied from 4.7 Hz to 4.8 kHz.

The device has two digital filter options. The choice of filter

affects the rms noise/noise-free resolution at the programmed

output data rate, the settling time, and the 50 Hz/60 Hz rejec-

tion. For applications that require all conversions to be settled,

the AD7195 includes a zero latency feature.

The part operates with a 5 V analog power supply and a digital

power supply from 2.7 V to 5.25 V. It consumes a current of

6 mA. It is housed in a 32-lead LFCSP package.

DGND

REFIN(+) REFIN(–)

REFERENCE

INTERFACE

Σ-Δ

PGA

ADC

EXCITATION

CLOCK

ACX1

ACX2

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

DETECT

DOUT/RDY

SERIAL

DIN

AND

CONTROL

SCLK

LOGIC

SYNC

CLOCK

CIRCUITRY

MCLK1 MCLK2

AD7195

www.analog.com

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Summary of Contents for Analog Devices AD7195

Page 1: Features
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Page 2: Table Of Contents
AD7195 TABLE OF CONTENTS Features ....................1 Overview ..................25 Interface ..................... 1 Analog Input Channel ............... 26 Applications ..................1 PGA ....................26 General Description ................. 1 Reference ..................26 ...
Page 3: Specifications
AD7195 SPECIFICATIONS = 4.75 V to 5.25 V, DV = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFIN(+) = AV , REFIN(−) = AGND, MCLK = 4.92 MHz, to T , unless otherwise noted. Table 1.
Page 4 AD7195 Parameter Unit Test Conditions/Comments External Clock @ 50 Hz, 60 Hz 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz 50 Hz output data rate, REJ60 = 1, 50 ± 1 Hz, 60 ± 1 Hz @ 50 Hz 50 Hz output data rate, 50 ±...
Page 5 AD7195 Parameter Unit Test Conditions/Comments LOGIC INPUTS Input High Voltage, V Input Low Voltage, V Hysteresis 0.25 Input Currents −10 μA LOGIC OUTPUT (DOUT/ RDY ) Output High Voltage, V − 0.6 = 3 V, I = 100 μA SOURCE...
Page 6: Timing Characteristics
AD7195 TIMING CHARACTERISTICS = 4.75 V to 5.25 V, DV = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DV , unless otherwise noted. Table 2. 1, 2...
Page 7 AD7195 Circuit and Timing Diagram (1.6mA WITH DV = 5V, SINK 100µA WITH DV = 3V) OUTPUT 1.6V 50pF (200µA WITH DV = 5V, SOURCE 100µA WITH DV = 3V) Figure 2. Load Circuit for Timing Characterization CS (I) DOUT/RDY (O)
Page 8: Absolute Maximum Ratings
AD7195 ABSOLUTE MAXIMUM RATINGS = 25°C, unless otherwise noted. THERMAL RESISTANCE θ is specified for the worst-case conditions, that is, a device Table 3. soldered in a circuit board for surface-mount packages. Parameter Rating to AGND −0.3 V to +6.5 V Table 4.
Page 9: Pin Configuration And Function Descriptions
AD7195 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ACX2 ACX2 ACX1 DGND AD7195 ACX1 AGND TOP VIEW BPDSW (Not to Scale) AGND REFIN(–) REFIN(+) AINCOM NOTES 1. NC = NO CONNECT. 2. CONNECT EXPOSED PAD TO AGND. Figure 5.Pin Configuration Table 5. Pin Function Descriptions Pin No.
Page 10 Master Clock Signal for the Device. The AD7195 has an internal 4.92 MHz clock. This internal clock can be made available on the MCLK2 pin. The clock for the AD7195 can be provided externally also in the form of a crystal or external clock.
Page 11: Typical Performance Characteristics
AD7195 TYPICAL PERFORMANCE CHARACTERISTICS 8,388,760 8,388,758 8,388,756 8,388,754 8,388,752 8,388,750 8,388,748 8,388,746 1000 8,388,490 8,388,576 8,388,662 8,388,748 8,388,834 8,388,920 SAMPLE CODE Figure 6. Noise (V = 5 V, Output Data Rate = 4.7 Hz, Gain = 128, Figure 9. Noise Distribution Histogram (V...
Page 12 AD7195 –0.1 –0.2 –0.3 –0.4 –1.0 –0.5 –2.0 –0.6 –3.0 –0.7 –2.5 –2.0 –1.5 –1.0 –0.5 –60 –40 –20 TEMERATURE (°C) Figure 12. INL (Gain = 1) Figure 15. Offset Error (Gain = 128, Chop Disabled) 1.000008 1.000007 1.000006 1.000005 1.000004...
Page 13: Rms Noise And Resolution
(peak-to-peak) resolu- is continuously converting on a single channel. It is important tion of the AD7195 for various output data rates and gain settings, to note that the effective resolution is calculated using the rms...
Page 14: Sinc 3 Chop Disabled
AD7195 SINC CHOP DISABLED Table 9. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64...
Page 15: Sinc 4 Chop Enabled
AD7195 SINC CHOP ENABLED Table 12. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64...
Page 16: Sinc 3 Chop Enabled
AD7195 SINC CHOP ENABLED Table 15. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64...
Page 17: On-Chip Registers
AD7195 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers described on the following pages. In the following descriptions, the term set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted.
Page 18: Communications Register
AD7195 COMMUNICATIONS REGISTER state of the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to (RS2, RS1, RS0 = 0, 0, 0) the communications register. In situations where the interface The communications register is an 8-bit write-only register.
Page 19: Status Register
AD7195 STATUS REGISTER (RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80) The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 21 outlines the bit designations for the status register.
Page 20 MR19, MR18 CLK1, CLK0 These bits select the clock source for the AD7195. Either the on-chip 4.92 MHz clock or an external clock can be used. The ability to use an external clock allows several AD7195 devices to be synchro- nized.
Page 21: Configuration Register
Idle mode. In idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks are still provided. Power-down mode. In power-down mode, all AD7195 circuitry, except the bridge power-down switch, is powered down. The bridge power-down switch remains active because the user may need to power up the sensor prior to powering up the AD7195 for settling reasons.
Page 22 CON22 AC excitation enable bit. If the signal source to the AD7195 is ac excited, this bit must be set to 1. For dc-excited inputs, this bit must be 0. With the ACX bit at 1, the AD7195 assumes that the voltage at the AIN(+)/AIN(–) and REFIN(+)/REFIN(–) input terminals are reversed on alternate input sampling cycles...
Page 23: Data Register
ID REGISTER (RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xA6) The identification number for the AD7195 is stored in the ID register. This is a read-only register. GPOCON REGISTER (RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00) The GPOCON register is an 8-bit register from which data can be read or to which data can be written.
Page 24: Offset Register
= 1. Therefore, every device has different default coeffic- initiated by the user. The AD7195 must be placed in power- ients. The default value is automatically overwritten if an down mode or idle mode when writing to the offset register.
Page 25: Adc Circuit Information
OVERVIEW The AD7195 contains a fourth-order Σ-Δ modulator followed The AD7195 is an ultralow noise ADC that incorporates a Σ-Δ by a digital filter. The device offers the following filter options: modulator, a buffer, PGA, and on-chip digital filtering intended •...
Page 26: Analog Input Channel
In this case, the NOREF The AD7195 can be programmed to have a gain of 1, 8, 16, 32, bit of the status register is set to 1. If the AD7195 is performing 64, and 128 using Bit G2 to Bit G0 in the configuration register.
Page 27: Bipolar/Unipolar Configuration
AIN1 pin is 2.5 V to 3.75 V when a 2.5 V AC EXCITATION reference is used. If AINCOM is 2.5 V and the AD7195 AIN1 AC excitation of the bridge addresses many of the concerns...
Page 28: Channel Sequencer
When the ACX bit in the configuration register is set to 0, and the RDY pin is taken high. The AD7195 then allows the the digital outputs ACX1 and ACX2 are high, while outputs complete settling time to generate the first conversion.
Page 29 The serial interface can be reset by writing a series of 1s to the enabled channels and performs a conversion on each channel. DIN input. If a Logic 1 is written to the AD7195 DIN line for When a conversion is started, DOUT/ RDY goes high and at least 40 serial clock cycles, the serial interface is reset.
Page 30 Continuous conversion is the default power-up mode. The on each channel per loop. The data register is updated as soon AD7195 converts continuously, and the RDY bit in the status as each conversion is available. The DOUT/ RDY pin pulses low register goes low each time a conversion is complete.
Page 31 Rather than write to the communications register each time a conversion is complete to access the data, the AD7195 can To exit the continuous read mode, Instruction 01011000 must be configured so that the conversions are placed on the be written to the communications register while the RDY pin DOUT/ RDY line automatically.
Page 32: Reset
AD7195 RESET the AD7195. The clock source is selected using the CLK1 and CLK0 bits in the mode register. When an external crystal is The circuitry and serial interface of the AD7195 can be reset used, it must be connected across the MCLK1 and MCLK2 by writing consecutive 1s to the device;...
Page 33: Bridge Power-Down Switch
MD0 bits. The DOUT/ RDY pin and the RDY bit in the status The gain error of the AD7195 is factory calibrated at a gain of 1 register go high when the calibration is initiated. When the with a 5 V power supply at ambient temperature.
Page 34: Digital Filter
When conversions are performed on a single channel and a step change occurs, the ADC does not detect the change in The AD7195 offers a lot of flexibility in the digital filter. The analog input. Therefore, it continues to output conversions device has four filter options.
Page 35 AD7195 When the analog input is constant or a channel change occurs, Figure 29 shows the frequency response when FS[9:0] is valid conversions are available at a constant output data rate. programmed to 80 and the master clock is equal to 4.92 MHz.
Page 36: Sinc 3 Filter (Chop Disabled)
AD7195 The output data rate is 50 Hz when zero latency is disabled and The 3 dB frequency is equal to 12.5 Hz when zero latency is enabled. Figure 31 shows the = 0.272 × f frequency response of the sinc filter.
Page 37 AD7195 The output data rate equals Sinc 50 Hz/60 Hz Rejection Figure 36 show the frequency response of the sinc filter when = 1/t /(3 × 1024 × FS[9:0]) SETTLE FS[9:0] is set to 96 and the master clock equals 4.92 MHz. The...
Page 38: Chop Enabled (Sinc Filter)
AD7195 Simultaneous 50 Hz and 60 Hz rejection is obtained when CHOP ENABLED (SINC FILTER) FS[9:0] is set to 480 (master clock = 4.92 MHz), as shown in With chop enabled, the ADC offset and offset drift are minimized. Figure 38. The output data rate is 10 Hz when zero latency is The analog input pins are continuously swapped.
Page 39 AD7195 When a channel change occurs, the modulator and filter reset. –10 The complete settling time is required to generate the first –20 conversion after the channel change. Subsequent conversions –30 on this channel occur at 1/f –40 –50 CHANNEL A...
Page 40: Chop Enabled (Sinc Filter)
AD7195 CHOP ENABLED (SINC FILTER) If conversions are performed on a single channel and a step change occurs, the ADC does not detect the change in analog With chop enabled, the ADC offset and offset drift are input; therefore, it continues to output conversions at the minimized.
Page 41: Summary Of Filter Options
SUMMARY OF FILTER OPTIONS REJ60 bit in the mode register to 1. With FS[9:0] set to 96 and The AD7195 has several filter options. The filter that is chosen REJ60 set to 1, the filter response shown in Figure 49 is achieved.
Page 42: Grounding And Layout
AD7195 to prevent noise coupling. The power multiples of the modulator sampling frequency. supply lines to the AD7195 must use as wide a trace as possible Connect an R-C filter to each analog input pin to provide to provide low impedance paths and reduce the effects of glitches on the power supply line.
Page 43: Applications Information
AC excitation is enabled by setting Bit ACX in the configuration register to 1. When the ACX bit is set to 0, the bridge is dc Figure 50 shows the AD7195 being used in a weigh scale applica- excited. When the AD7195 is in power-down mode, the bridge tion which uses ac excitation.
Page 44: Outline Dimensions
AD7195BCPZ-RL7 –40°C to +105°C 32-Lead LFCSP_WQ CP-32-11 Z = RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08771-0-1/10(0) Rev. 0 | Page 44 of 44 Downloaded from Elcodis.com...

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Analog Devices AD7195 Manual

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FEATURES

INTERFACE

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

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