Analog Devices ADRV9005 Reference Manual page 72

Reference Manual
DATA INTERFACE
Figure 49 shows the transmit CMOS SSI with DDR clock in relation to the strobe/data, with respect to the ADRV9001. Each edge of the clock
(positive and negative) samples the corresponding strobe/data sample based on the interface setup/hold timing.
When the baseband processor drives out the transmit SSI clock, strobe, and data to the ADRV9001, the output DDR clock can either be
in-phase with the strobe/data or delayed by a quarter cycle of the clock period. Regardless of the choice, the relationship between the transmit
DDR clock and strobe/data must meet the ADRV9001 setup and hold timing specification.
Figure 50 and Figure 51 show the timing diagram examples for four-lane mode receive and transmit CSSI with DDR clock and 16-bit I/Q
samples.
analog.com
Figure 48. Receive CSSI DDR Clock Relation with Strobe/Data
Figure 49. Transmit CSSI DDR Clock Relation with Strobe/Data
Figure 50. Four-Lane Mode Receive CSSI DDR Timing for 16-Bit I/Q Data Sample
ADRV9001
Rev. A | 72 of 377