Adrv9003; Adrv9004; Adrv9005; Adrv9006 - Analog Devices ADRV9005 Reference Manual

Reference Manual
PRODUCT HIGHLIGHTS
The ADC in the receive chain possesses a high dynamic range. Assuming 0 dB attenuation, the ADC's noise and maximum input power
referred to the RF input are -142 dBm/Hz and 8.6 dBm, respectively. These levels translate into a dynamic range in excess of 150 dB on a per
Hertz basis. A greater dynamic range can be achieved by considering the digital filtering and AGC loops.
Given the high dynamic range of the receiver ADC, very little channelization, or blocker filtering occurs in the analog signal chain as the ADC
can simultaneously absorb weak signals and large blockers. The blocker suppression and channelization are then achieved in the digital signal
path.
Reciprocal mixing of the RX LO phase noise by a large blocker close to the desired channel significantly degrades the blocking performance. If
high blocker tolerance performance is required, use a lower phase noise external LO source in place of the on-board RFPLLs.
The receiver path also contains two types of ADCs connected to the chip's RF front end for tradeoff between power consumption and dynamic
range: a high performance ADC with high linearity performance and a low power ADC with degraded linearity performance but less power
consumption. Trade off receive channel linearity performance and power consumption by selecting either set of ADCs.
Power Consumption Modes
The ADRV9002 provides various levels of power control. The power scaling on individual analog signal path blocks can trade-off power and
performance. In addition, enabling and disabling various blocks in TDD RX and TX frames to reduce power can be customized, at the expense
of RX/TX or TX/RX turnaround time.
A specialized "RX Monitor mode" allows the
a low power state. In this mode, the chip continuously cycles through sleep-detect-sleep states controlled by an internal state machine. The
power savings are achieved by ensuring the sleep duty cycle is greater than the "detect" duty cycle.
In the "sleep" state, the chip is in a minimal power consumption configuration with only few functions enabled, and it also allows the baseband
process to go to sleep. After a predetermined period, the chip enters the "detect" state. In this state, the chip enables a receiver and performs
signal detection over a bandwidth and at an RX LO frequency determined by the user. If a signal is detected, the "Monitor Mode" state machine
exits its cycle. Following the loop exit, an interrupt is provided through a GPIO pin to wake the baseband processor, and the entire receiver
analog and digital chains within the
If the power measured over the bandwidth is less than the user-determined threshold, the chip resumes its sleep-detect-sleep cycle. The
sleep-detect duty cycle and durations and signal detection method are user-programmable, and are set before enabling the monitor mode.

ADRV9003

The ADRV9003 delivers all the features and performance of the
ADRV9003 are:
RF IOs. The ADRV9003 has two receivers and one transmitter.
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The ADRV9003 does not support the digital predistortion functionality.
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ADRV9004

The ADRV9004 delivers all features and performance of the
The ADRV9004 does not support the digital predistortion functionality.
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ADRV9005

The ADRV9005 delivers all the features and performance of the ADRV9002 transceiver. The differences between the ADRV9002 and the
ADRV9005 are the following:
RF IOs. The ADRV9005 has one receiver and one transmitter.
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Tx Tracking calibrations can only be performed in TDD mode. Not available in FDD mode.
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ADRV9006

The differences between the ADRV9002 and the
The ADRV9006 only supports the frequency hopping functionality with 'normal' speed.
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ADRV9002 to autonomously poll a region of the spectrum for the presence of a signal while in
ADRV9002 are powered up.
ADRV9002
ADRV9002
ADRV9006 are as follows:
transceiver. The differences between the
transceiver. The difference between the
ADRV9001
ADRV9002 and
ADRV9002 and ADRV9004 is:
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