Analog Devices ADRV9005 Reference Manual page 71

Reference Manual
DATA INTERFACE
RX_QDATA3_OUT: output serial data stream of Q sample high byte.
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Figure 46 shows the receive CSSI (Rx1 and Rx2) for a four-lane format with MSB first configuration.
The four-lane mode CSSI transmits the interface of each channel (Tx1 and Tx2). This is a 7-wire digital interface consisting of:
TX_DCLK_IN: input clock synchronized to the data and strobe inputs.
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TX_STROBE_IN: input signal indicating the first bit of the serial data sample.
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TX_IDATA0_IN: input serial data stream of I sample low byte.
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TX_IDATA1_IN: input serial data stream of I sample high byte.
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TX_QDATA2_IN: input serial data stream of Q sample low byte.
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TX_QDATA3_IN: input serial data stream of Q sample high byte.
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TX_DCLK_OUT: optional output reference clock provided to the baseband processor to generate all the above signals. The baseband
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processor can also use RX_DCLK_OUT as the reference clock when its clock rate is equal to the transmit SSI clock rate.
Figure 47 shows the transmit CSSI (Tx1 and Tx2) for a four-lane format with MSB first configuration.
Transmit and Receive CSSI Using DDR Clock
Transmit and receive CSSI can be operated in either SDR or DDR data transfer.
Figure 48 shows the Rx CMOS SSI with DDR clock in relation to the strobe/data. Each edge of the clock (positive and negative) corresponds
to a data sample. The RX DDR clock can be generated in phase with the data/strobe or delayed by a quarter cycle of the clock period. The
optional delayed clock eases the timing interface of the baseband processor to meet the setup/hold on the baseband processor.
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Figure 46. Four-Lane Mode Receive CSSI Timing for 16-Bit I/Q Data Sample (MSB First)
Figure 47. Four-Lane Mode Transmit CSSI Timing for 16-Bit I/Q Data Sample (MSB First)
ADRV9001
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