Analog Devices ADRV9005 Reference Manual page 204

Reference Manual ADRV9001
RECEIVER GAIN CONTROL
applied. The interface gain is determined by RSSI. If the power level is too high, the slicer shifts the signal properly before sending it to the data
port to avoid saturation.
Let us look at a slicer example that considers three different input signal power levels. The power level 1 fits a data length of 16 bit-width. Power
level 2 is 0 dB to 6 dB higher than power level 1, which increases the bit-width by 1. Power level 3 is 6 dB to 12 dB higher than power level 1,
which further increases bit-width by 1. Figure 177 outlines this effect, with gray boxes indicating the valid (used) bits in each case.
Figure 177. Bit Width of Input Signal with Increasing Power Levels
The slicer is used to attenuate the data such that it can fit into the resolution of the data port. As the output is a shifted version of the input, the
slicer can only handle gains in ±6 dB steps.
Figure 178 explains the slicer operation. For power level 1, the slicer shift value is calculated as 0, so the 16-bit output data is taken from D15 –
D0. As the power level increases, the bit-width of the signal increases. For power level 2, now the bit-width is 17. The slicer shift value becomes
1, so the 16-bit output data is taken from D16 – D1. This is equivalent to applying 6 dB of attenuation by a slicer, which ensures that the
bit-width of the signal is 16 once more; i.e., the 16 MSBs are selected (sliced) with the LSB dropped. When the power level further increases, as
power level 2, the signal bit-width becomes 18-bit. The slicer shift value becomes 2, so the 16-bit output data is taken from D17 – D2, which is
equivalent to applying 12 dB of attenuation by slicer, or slice the 16 MSBs dropping the 2 LSBs.
Figure 178. Slicer Bit Selection with Different Input Power Levels
The slicer algorithm assumes a max PAR of 15 dB, and it adjusts the interface gain such that the measured signal power +15 dB is less than a
predefined threshold such as 0 dBFS. For NB applications, the interface gain is from −36 dB to +18 dB, and for WB applications, the interface
gain is from −36 dB to 0 dB in 6 dB step size.
Similarly, the baseband processor retrieves the interface gain through API commands to scale the power of the received signal to determine the
power at the input to the device (or at the input to an external gain element if included as a part of the digital gain compensation).
Mode 4: Digital Gain Compensation with External Interface Gain Control
This mode is similar to mode 3, except the interface gain is controlled by selecting a proper value. The baseband processor measures the
input signal power or uses the power measurement done by RSSI in the device to determine the interface gain. Then, through API commands,
the slicer operates in the same way as mentioned in mode 3. For NB applications, the interface gain is from −36 dB to +18 dB, and for WB
applications, the interface gain is from −36 dB to 0 dB in 6 dB step size. Use this mode especially when the baseband processor input signal
clipping is observed.
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