Analog Devices ADRV9005 Reference Manual page 74

Reference Manual
DATA INTERFACE
The RX_STROBE signal is aligned with the first bit of the serialized data (I and Q), and can be configured to be high:
For a half-clock cycle at the start of I and Q sample transmit. For a 16-bit data sample, RX_STROBE is high for a half-clock cycle and low for
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a half and 15 clock cycles. For a 12-bit data sample, RX_STROBE is high for a half-clock cycle and low for a half and 11 clock cycles.
For half of I and Q data duration. For a 16-bit data sample, the RX_STROBE is high for 4 clock cycles, and low for 4 clock cycles (Q data
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sample). For a 12bit data sample, the RX_STROBE is high for 3 clock cycles and low for 3 clock cycles.
In the 12-bit I/Q mode, 16-bit samples from the receive datapath are cut to 12 bits for LSSI, a configurable option to choose the 12-bit from the
LSB or MSB of the 16-bit sample data.
Receive LSSI with One-Lane for I and Q
In this mode, only one-lane is used to transfer I and Q data samples. The I/Q data bits are serialized with configurable I or Q first and MSB or
LSB first. The strobe signal can be configured to high for a half-clock cycle to indicate the start of I and Q symbols or for half of the I and Q data
duration to distinguish between I and Q data.
Figure 54 shows that the one-lane receives LSSI (Rx1 and Rx2) for a 16-bit I/Q data sample with the I sample and MSB first configuration.
Transmit LSSI
The transmit LSSI of each channel (Tx1 and Tx2) is an 8-wire digital interface consisting of:
TX_DCLK_IN (±): is a differential input clock synchronized to the data and strobe inputs.
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TX_STROBE_IN (±): is a differential input signal indicating the first bit of the serial data sample.
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TX_IDATA_IN (±): is a differential input serial I data stream.
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TX_QDATA_IN (±): is a differential input serial Q data stream.
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An additional port can used as a reference clock for the baseband processor to generate the transmit LSSI clock, strobe, and data signal. Use
RX1_DCLK_OUT or RX2_DCLK_OUT as a reference clock if these clock frequencies are equal to the TX clock frequency.
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Figure 53. Receive LSSI Timing for 12-Bit I/Q Data Sample over Two Lanes (MSB First)
Figure 54. Receive LSSI Timing for 16-Bit I/Q Data Sample over One-Lane (I and MSB First)
ADRV9001
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