Analog Devices ADRV9005 Reference Manual page 130

Reference Manual
FREQUENCY HOPPING
Table 55. PLL Retune Time (PLL Calibration Mode = Normal) (Continued)
Device Clock (MHz)
150 275.7
200 256
245.76 252.1
300 267.2
The table above shows the measured PLL retune time, where 'std.' means the standard deviation. Note the required retune time reduces with
the increase of the device clock frequency (PFD). Both 'Fast Calibration' and 'Normal Calibration' modes are provided. 'Fast Calibration' mode
reduces the retune time but has limited temperature tracking. 'Normal Calibration' mode increases the retune time but has full temperature
tracking. 'Normal Calibration' mode should only be used in cases of a long frame time where temperature might change significantly. The PLL
loop bandwidth is another configurable parameter of the PLL. A loop BW of 1200 k was found to give optimal retune timing for fast calibration
mode.
Note: the PLL retune time is defined as the time from the start of PLL retuning until the time when the PLL settles within 500 Hz of the settled
frequency.
PLL Retune Measurement
The PLL retune time can be measured by observing the PLL settling time between two consecutive Tx frames. A summary of the measurement
is given in this section. An illustration of two consecutive Tx frames in
signals as well as the 'Tx On Air' for a FH LO retune case. Note that t
The goal of the measurement will be to measure the transition time as shown in
1. Two consecutive Tx frames are used. The full frame time should be at least t
should be set to 0. For example, for a 38.4 MHz device clock, 300 kHz loop BW, and using fast calibration mode, the minimum frame time
would be 83.5 µs + 20 µs = 103.5 µs. Some margin should be added to clearly see the 'on air' time. Ensure to align Tx DMAs correctly or
simply have DMAs always on. Otherwise, the Tx datapath could be on but no Tx data is propagating through. See the
Timing section for further details on the timing parameters.
2. Configure the FH with 'LO retune mode'. Start the FH operation and ensure that the operation works as expected. 'LO retune mode' is used
to view the transition time clearly. All other modes will have the same t
3. Connect the Tx output to a spectrum analyzer with a time overview mode and frequency settling mode. Trigger the capture using the hop
edge for best results. Ensure that the frame timing is as expected using the time overview mode.
4. Enter the frequency settling mode. The retune time can be measured by observing the time it takes to settle the PLL/Tx output. Set the
frequency tolerance to +/− 500 Hz to match the above measured results or set desired limits. Measure the transition time by observing
the 'settling time' between two frames. The settling time is defined as the time between the Tx output leaving the defined limits until it
re-enters the defined limits. This is equivalent to the transition time. t
µs).
Example: the following capture was taken of a FH transition time for the following criteria: 38.4 MHz device clock, 300 kHz loop BW, fast
calibration mode. A FH table was constructed with two entries where the frequencies were similar (1 Hz apart) and the Tx attenuation was
analog.com
PLL Loop BW = 1200 kHz
Average (µs)
55.2
37.3
38
62.1
Figure 121. Measuring PLL Retune Time Timing Diagram
Std. (µs) Average (µs)
293.5
274.4
269.1
265.4
Figure 121 shows the relationship between the 'Hop' and 'Tx Setup'
is the sum of t
transition FHProcess
Figure 121. The general method is as follows:
+ t
pllRetune FHProcessing
.
pllRetune
can then be calculated as t
pllRetune
ADRV9001
PLL Loop BW = 300 kHz
Std. (µs)
38.7
30.1
35.8
53.6
and t .
pllRetune
(based on Table 54) and t
chRiseToAnaOn
Frequency Hopping
(measured) − t
transition FHProcess
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