Analog Devices ADRV9005 Reference Manual page 146

Reference Manual ADRV9001
TRANSMITTER SIGNAL CHAIN
GPIO Mode
The general purpose input/output (GPIO) mode is another method to control the transmitter attenuation block. In this mode, two GPIO pins are
used to increment or decrement the current attenuation value. An API command "adi_adrv9001_Tx_Attenuation_PinControl_Configure()"
configures the GPIO pins and sets the step size. Figure 142 shows a typical output power transient.
Figure 142. GPIO Increment/Decrement Mode
Power Amplifier Protection
In the transmitter signal chain, two power amplifier protection mechanisms protect the power amplifier from excessive peak or average power
excursions. Note that the current release does not fully support these features.
Power Monitor
The power monitor is one of those power amplifier protection methods, and it uses the transmitter attenuation block to adjust the power by
continuously monitoring the output power of the Tx datapath.
Through API commands, enable power monitor and set configuration parameters such as average and peak power thresholds. The average
power is accumulated over a specified integration time, and an error flag is asserted if it exceeds the threshold. In addition, the instantaneous or
peak power is detected, and the error flag is asserted if a specified number of peaks is exceeded. Read the power amplifier error flag through
an API command. The power delivered to the power amplifier is automatically reduced if the error flag is asserted. In the scenario depicted in
Figure 143, the error flag is asserted after two power peaks are detected. The power amplifier power is automatically ramped down to maximum
attenuation. Note that the average power also exceeds its threshold, but not for long enough.
Figure 143. Power Amplifier Monitor
Slew Rate Limiter (SRL)
The slew rate limiter is the other method for power amplifier protection. It essentially limits the rate of change of a waveform by continuously
monitoring the difference between the input and output of the block and limiting the amount of output that can change during one cycle. As a
result, sudden changes in the input spread to the output over several cycles or symbols. Through API commands, control this slew limit as a
fraction of full-scale, which can be varied from very strong slew limiting to no slew limiting at all. For example, if the slew limit is set to 10%
full-scale, a full-scale step input to the step limiter results in a ramp, which spreads over the next 10 clock cycles. Figure 144 shows the basic
block diagram of the implemented slew rate limiter. The figure shows that the output sample is looped back to subtract from the input sample to
decide the slew rate. Based on the slew limit selection, a proper scaling factor is applied to reduce the slew rate to the desired level.
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