Power Management Control/Status Register (Pmcsr) 0Xe0 - Toshiba TMPR4937 Manual

10.5.4 Power Management Control/Status Register (PMCSR)
15 14
Reserved
PMESTA
R/W1C
0x0
Bit Mnemonic Field Name
15 PMESTA PME Status
14:9 Reserved
8 PMEEN PME Enable
7:2 Reserved
1:0 PS Power State
9 8 7
PMEEN
R/W
0x0
Description
PME_Status (Default: 0x0)
Indicates the existence of a PME (Power Management Event) .
1: There is a PME.
0: There is no PME.
The value of this bit becomes "1" when Writing a "1" to the PME bit
(P2GCFG.PME) of the P2G Configuration Register.
This bit is cleared when the Host Bridge writes a "1". It is possible to signal
a PME* Clear Interrupt at this time.
PME_En (Default: 0x0)
Sets PME* signal assertion to enable or disable.
1: Enables assertion of the PME* signal.
0: Disables assertion of the PME* signal.
The PME_En set bit of the P2G Status Register (P2GSTATUS.PMEES) is
set when this bit is set. At this time, it is possible to signal the PME_En set
interrupt.
PowerState (Default: 0x0)
Sets the Power Management state.
The Power Management State Change bit (P2GSTATUS.PMSC) of the
P2G Status Register is set when the value of this field is changed. It also
becomes possible to generate a Power State Change Interrupt at this time.
The TX4937 can read the value of this field from the PowerState field
(PCISSTATUS.PS) of the Satellite Mode PCI Status Register.
00b: D0 (no change)
01b: D1 :Reserved
10b: D2 :Reserved
11b: D3hot
Figure 10.5.4 PMCSR Register
10-102
Chapter 10 PCI Controller
0xE0
2
Reserved
1 0
PS
R/W : Type
0x0 : Initial value
Read/Write
R/W1C
⎯
R/W
⎯
R/W