Toshiba TMPR4937 Manual page 169

Table 8.3.3 Channel Register Setting Restrictions During Dual Address Transfer
DMSARn[2:0]
Transfer Setting
DMSAIRn
Size
setting is 0
(DMCCRn.XFSZ)
or greater
1 Byte
***
2 Bytes **0
4 Bytes *00
8 Bytes,
4 / 8 Double Wods 000
(DMMCR.FIFUM[n]=0)
000
4 / 8 Double Words
***
(DMMCR.FIFUM[n]=1)
⎯
16 Double Words
32 Double Words
: When DMSAIRn is set to 0, read access from source device is performed only one time per
transmission specified by DMCCRn.XFSZ. For this reason, transfer can not be performed burst
transfer to the I/O device which performs FIFO operation.
‡: 8, 0, or -8 can be specified when the Destination Burst Inhibit bit (DMCCRn.DBINH) is set.
8.3.8.2 Burst Transfer During Dual Address Transfer
The DMA Controller has a 64-bit 8-stage FIFO on-chip that is connected to the internal bus (G-
Bus) for Burst transfer during Dual Address transfer. Since this FIFO employs a shifter, it is
possible to perform transfer of any address or data size. Burst transfer is only performed when 4
Double Words or 8 Double Words is set by the Transfer Setting Size field (DMCCRn.XFSZ) and
the FIFO Use Enable bit (DMMCRn.FIFUM[n]) of the DMA Master Control Register is set.
According to the SDRAM Controller and External Bus Controller specifications, the DMA
Controller cannot perform Burst transfer that spans across 32-double word boundaries.
Consequently, if the address that starts DMA transfer is not a multiple of the transfer setting size
(DMCCRn.XFSZ) (is not aligned), transfer cannot be performed by any of the transfer sizes that
were specified by a Burst transfer. Therefore, it is necessary to divide the transfer into multiple
Burst transactions of a transfer size smaller than the specified transfer size. This division method
changes according to the seting of the Transfer Size Mode bit (DMCCRn.USEXFSZ) of the DMA
Channel Control Register and whether or not the address offset relative to the Transfer Setting size
(DMCCRn.XFSZ) is equivalent to the source address and destination address combined.
Figure 8.3.3 shows Dual Address Burst transfer when the Transfer Size Mode bit
(DMCCRn.USEXFSZ) is set to "1", the lower 8 bits of the Transfer Start address for the transfer
source are set to 0xA8, the lower 8 bits of the Transfer Start address for the transfer destination are
set to 0x38, and the Transfer Setting Size (DMCCRn.XFSZ) is set to 8 Double Words.
Transfer repeats according to the transfer setting size, regardless of the different address offsets.
However, transfers that span across 32-double word boundaries are divided. Since data remains in
the on-chip FIFO when in this mode, it becomes possible to share the on-chip FIFO among
multiple DMA channels.
DMDARn[2:0]
DMSAIRn DMDAIRn
DMDAIRn
setting is a setting is a
setting is 0
negative negative
or greater
value value
*** ***
**0 **0
*00 *00
111 000
111 000
⎯
***
⎯
***
Cannot be set (Configuration Error)
Cannot be set (Configuration Error)
8-13
Chapter 8 DMA Controller
DMSAIRn DMDAIRn DMCNTRn
*** *** ***
**1 **0 **0
*11 *00 *00
111 000 000
111 8/0/-8 8/-8 ‡
⎯
8 8
-8 -8
***
DMCCRn
REVBYTE
0
***
**0 0
*00 0
000 0/1
000 0/1
0
***
0