Toshiba TMPR4937 Manual page 481

Bit Mnemonic Field Name
22 IS22 Interrupt Status 22
21 IS21 Interrupt Status 21
⎯
20
19 IS19 Interrupt Status 19
18 IS18 Interrupt Status 18
17 IS17 Interrupt Status 17
16 IS16 Interrupt Status 16
15 IS15 Interrupt Status 15
14 IS14 Interrupt Status 14
13 IS13 Interrupt Status 13
12 IS12 Interrupt Status 12
11 IS11 Interrupt Status 11
10 IS10 Interrupt Status 10
IRINTREQ [22] status
This bit indicates the PCIERR error status.
1: Interrupt requests
0: No interrupt requests
IRINTREQ [21] status
This bit indicates the NDFMC interrupt status.
1: Interrupt requests
0: No interrupt requests
⎯
Reserved
IRINTREQ [19] status
This bit indicates the TMR [2] interrupt status.
1: Interrupt requests
0: No interrupt requests
IRINTREQ [18] status
This bit indicates the TMR [1] interrupt status.
1: Interrupt requests
0: No interrupt requests
IRINTREQ [17] status
This bit indicates the TMR[0] interrupt status
1: Interrupt requests
0: No interrupt requests
IRINTREQ [16] status
This bit indicates the PCIC interrupt status
1: Interrupt requests
0: No interrupt requests
IRINTREQ [15] status
This bit indicates the PDMAC interrupt status.
1: Interrupt requests
0: No interrupt requests
IRINTREQ [14] status
This bit indicates the IRC interrupt status
1: Interrupt requests
0: No interrupt requests
IRINTREQ [13] status
This bit indicates the DMA [3] interrupt status
1: Interrupt requests
0: No interrupt requests
IRINTREQ [12] status
This bit indicates the status of DMA [2] interrupts.
1: Interrupt requests
0: No interrupt requests
IRINTREQ [11] status
This bit indicates the status of DMA [1] interrupts.
1: Interrupt requests
0: No interrupts requests
IRINTREQ [10] status
This bit indicates the status of DMA [0] interrupts.
1: Interrupt requests
0: No interrupt requests
Figure 15.4.14 Interrupt Source Status Register (2/3)
15-35
Chapter 15 Interrupt Controller
Explanation Read/Write
R
R
⎯
R
R
R
R
R
R
R
R
R
R