Interrupt Detection Mode Register 1 (Irdm1) 0Xf608 - Toshiba TMPR4937 Manual

15.4.3 Interrupt Detection Mode Register 1 (IRDM1)
31 30 29
IC31 IC30
R/W R/W
0 0
15 14 13
IC15 IC14
R/W R/W
0 0
Bit Mnemonic Field Name
31:30 IC31 Interrupt Source
Control 31
29:28 IC30 Interrupt Source
Control 30
Interrupt Source
27:26 IC29
Control 29
25:24 IC28 Interrupt Source
Control 28
23:22 IC27 Interrupt Source
Control 27
Interrupt Source
21:20 IC26
Control 26
28 27 26 25 24
IC29 IC28
R/W R/W
0 0
12 11 10 9 8
IC13 IC12
R/W R/W
0 0
Interrupt Source Control 31 (Default: 00, R/W)
These bits specify the active state of SPI interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 30 (Default: 00, R/W)
These bits specify the active state of DMA1[3] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 29 (Default: 00, R/W)
These bits specify the active state of DMA1[2] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 28 (Default: 00, R/W)
These bits specify the active state of DMA1[1] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 27 (Default: 00, R/W)
These bits specify the active state of DMA1[0] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 26 (Default: 00, R/W)
These bits specify the active state of PCIC1 interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Figure 15.4.3 Interrupt Detection Mode Register 1 (1/3)
15-14
Chapter 15 Interrupt Controller
0xF608
23 22 21 20 19
IC27 IC26
R/W R/W
0 0
7 6 5 4 3
IC11 IC10
R/W R/W
0 0
Explanation
18 17 16
IC25 IC24
R/W R/W : Type
0 0 : Default
2 1 0
IC9 IC8
R/W R/W : Type
0 0 : Default
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W