Error Detection/Interrupt Signaling - Toshiba TMPR4937 Manual

11.3.11 Error Detection/Interrupt Signaling

An interrupt is signaled if an error or an interrupt cause is detected, the corresponding status bit is set
and the corresponding Interrupt Enable bit is set.
The following figure shows the relationship between the status bit for each interrupt cause and each
interrupt enable bit. Please refer to the explanation for each status bit for more information about each
interrupt cause.
Transmission DMA Acknowledge
DMAC
Transmission DMA Request
To IRC
Reception DMA Acknowledge
DMAC
Transmission DMA Acknowledge
Figure 11.3.3 Relationship Between Interrupt Status Bits and Interrupt Signals
"0" Write
SIDICR.TDE
SIDICR.TIE
SIDISR.STIS
R
"0" Write
SIDISR.ERI
R
SIDICR.SPIE
"0" Write
SIDICR.RIE
SIDICR.RDE
"0" Write
11-10
Chapter 11 Serial I/O Port
R
SIDSR.TDIS
SISCISR.OERS
SIDICR.STIE[5]
R
"0" Write
SISCISR.CTSS CTS Pin
SIDICR.STIE[4]
S
SIDICR.CTSAC
SISCISR.RBRKD
SIDICR.STIE[3]
SISCISR.TRDY
SIDICR.STIE[2]
SISCISR.TXALS
SIDICR.STIE[1]
SISCISR.UBRKD
SIDICR.STIE[0]
R
"0" Write
SIDISR.TOUT
R
"0" Write
SIDISR.RDIS
R
Transmission Data Empty
Overrun Error
CTS Status
During Break Reception
Transmission Data Empty
Transmission Complete
Break Detected
Frame Error
Parity Error
Reception Time Out
Reception Data Full