Pdmac Configuration Register (Pdmcfg) 0Xd220 - Toshiba TMPR4937 Manual

10.4.62 PDMAC Configuration Register (PDMCFG) 0xD220

63
47
31
15 14 13
Reserved REQDLY
R/W
0x0
Bit Mnemonic Field Name
63:22 Reserved
21 RSTFIFO Reset FIFO
20 EXFER Endian Transfer
19:14 Reserved
Request Delay
13:11 REQDLY
Time
10 ERRIE Error Detect
Interrupt Enable
9 NCCMPIE Normal Chain
Complete
Interrupt Enable
Reserved
Reserved
Reserved
11 10 9 8
ERRIE
CHNEN
NCCMPIE NTCMPIE
R/W R/W R/W
0x0 0x0 0x0 0x0
Reset FIFO (Default: 0x0)
Initializes the Read pointer and Write pointer to the FIFO in the PDMAC,
and sets the FIFO hold count to "0". Please use the software to clear this
bit when it is set.
This is a function for a diagnosis. Usually, it is not used.
1: Performs FIFO reset.
0: Does not perform FIFO reset.
Endian Transfer (Default: 0x0)
Specifies whether to perform Endian transfer. Please use the default as is.
Set up EXFER as follows according to a Endian setup of G-Bus.
1: G-Bus in Little Endian
0: G-Bus in Big Endian
Request Delay (Default: 0x0)
G-Bus transactions for DMA transfer must be performed separated at least
by the interval this field specifies.
000: Continuously try to perform G-Bus transfer.
001: 16 G-Bus clocks
010: 32 G-Bus clocks
011: 64 G-Bus clocks
100: 128 G-Bus clocks
101: 256 G-Bus clocks
110: 512 G-Bus clocks
111: 1024 G-Bus clocks
Interrupt Enable on Error (Default: 0x0)
1: PDMAC generates an error during error detection.
0: PDMAC does not generate an error during error detection.
Interrupt Enable on Chain Done (Default: 0x0)
1: PDMAC generates an interrupt when the current chain is complete.
0: PDMAC does not generate an interrupt when the current chain is
complete.
Figure 10.4.60 PDMAC Configuration Register (1/2)
10-93
Chapter 10 PCI Controller
22 21 20 19
EXFER
RSTFIFO
R/W R/W
0x0 0x0
7 6 5 4
BSWAP
XFRACT Reserved
R R/W R/W
0x0 0x0
Description
48
: Type
: Initial value
32
: Type
: Initial value
16
Reserved
: Type
: Initial value
3 2 1 0
XFRSIZE CHRST
XFRDIRC
R/W R/W R/W : Type
0x0 0x0 0x1 : Initial value
Read/Write
⎯
R/W
R/W
⎯
R/W
R/W
R/W