Toshiba TMPR4937 Manual page 267

When expressed as a formula, conversion of a G-Bus address (GBusAddr[35:0]) into a PCI Bus
Address (PCIAddr[39:0]) is as follows below. GBASE[35:8], PBASE[39:8], and AM[35:8] each
represent the setting register of the corresponding access window indicated below in Table 10.3.2. The
"&" symbol indicates a logical AND for each bit, "||" indicates a logical OR for each bit, "!" indicates
logical NOT, and "|" indicates bit linking.
If (GBusAddr[35:8] & ! AM[35:8] == GBASE[35:8] & ! AM[35:8]) then
PCIAddr[39:0] = PBASE[39:36]
| ((PBASE[35:8] & ! AM[35:8]) || (GBusAddr[35:8] & AM[35:8]))
| GBusAddr[7:0];
Table 10.3.2 Initiator Access Space Address Mapping Register
G-Bus Base Address
GBASE[35:8]
Memory Space 0 G2PM0GBASE.BA[35:8]
Memory Space 1 G2PM1GBASE.BA[35:8]
Memory Space 2 G2PM2GBASE.BA[35:8]
I/O Space G2PIOGBASE.BA[35:8]
Figure 10.3.4 illustrates this address conversion.
GBusAddr
GBASE
AM
39
PBASE
39
PCIAddr
Figure 10.3.4 Address Conversion For Initiator (G-Bus → PCI Bus Address Conversion)
It is possible to set each space to valid/invalid or to perform Word Swap (see "10.3.7 Endian
Switching Function). Table 10.3.3 shows the settings registers for these properties.
When 64-bit access is made to the initiator memory space, two 32-bit Burst accesses are issued on the
PCI Bus. 64-bit access to the I/O space is not supported.
Also, operation is not guaranteed if resources in the PCI space were made cacheable and were then
accessed when the Critical Word First function of the TX49/H3 core was enabled.
PCI Bus Base Address
PBASE[39:8]
G2PM0PBASE.BA[39:8]
G2PM1PBASE.BA[39:8]
G2PM2PBASE.BA[39:8]
G2PIOPBASE.BA[39:8]
35
Compare
35
35
0 0 0 - - - - - - - - - - - 0 0 1 1 1 - - - - - - - - - - - - - - - - - - - -
10-9
Chapter 10 PCI Controller
Address Mask
AM[35:8]
G2PM0MASK.AM[35:8]
G2PM1MASK.AM[35:8]
G2PM2MASK.AM[35:8]
G2PIOMASK.AM[35:8]
8 7
0x00
8 7
0x00
8 7
0x00
0
0
0
0
0