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9.3.10.4 ECC Memory Access
8-bit check code is used whether the data bus width is 64 bits or 32 bits. For 32-bit data bus
width, check code is generated for and the error check is performed on 64-bit data that consists of
two 32-bit data at the double word boundary.
CB[7:0] are used for check code reading and writing when in the 64-bit mode. CB[3:0] are used
for check code reading and writing when in the 32-bit mode. An 8-bit check code is used for 64-
bit data. Similar to the data however, accesses to the memory are divided into half with 4 bits
being accessed at a time. The upper 4 bits of the check code are accessed simultaneous to when
the upper 32 bits of the data are written or read. Similarly, the lower 4 bits of the check code are
accessed simultaneous to when the lower 32 bits of the data are written or read.
All 64-bit data are always read and checked when set in the EC mode, ECC mode, or ECC +
Scrub mode. Consequently, data at the double word boundary, including this data, is read and
checked even when accessing data smaller than a double word (word access, byte access, etc.).
Read-Modify-Write (RMW) is performed during a Write operation of less than a double word.
First, 64 bits of data that include the address where the writing is performed is read. Then, check
code is generated for new 64-bit data that has replaced the written data.
Single-bit errors are corrected, but multi-bit errors are not. Therefore, if multi-bit errors are
detected, no data are written back to memory.
If data is being transferred between external I/O and memory during a DMAC single address
transfer, check code will not be generated even if the ECC function has been enabled.
9.3.10.5 Diagnostic Mode
Setting the Diagnostic Mode bit (ECCCR.DM) of the ECC Control Register makes it possible
to use the Diagnostic Mode. When in this mode and writing to a channel for which the ECC
function is enabled, the code that is set in the Diagnostic ECC field (ECCCR.DECC) is written in
place of the code that was calculated from the Write data.
Chapter 9 SDRAM Controller
9-16
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