G2P Memory Space 0 G-Bus Base Address Register (G2Pm0Gbase) 0Xd120 - Toshiba TMPR4937 Manual

10.4.31 G2P Memory Space 0 G-Bus Base Address Register (G2PM0GBASE)
63
47
31
15
BA[15:8]
R/W
0x00
Bit Mnemonic Field Name
63:38 Reserved
37 BSWAP Byte Swap
36 EXFER Endian Transfer
35:8 BA[35:8] Base Address
7:0 Reserved
Figure 10.4.29 G2P Memory Space 0 G-Bus Base Address Register
Reserved
Reserved
BA[31:16]
R/W
0x0000
8
Byte Swap Disable
(Default: Little Endian Mode: 0x1; Big Endian Mode: 0x0) Sets the byte
swapping of Memory Space 0.
1: Do not perform byte swapping.
0: Perform byte swapping.
Please use the default state in most situations. If this bit is changed to "1"
when in the Big Endian Mode, the byte order of transfer to Memory Space
0 through DWORD (32-bit) access will not change.
Endian Transfer
(Default: Little Endian Mode: 0x0; Big Endian Mode: 0x1)
Sets the Endian Transfer of Memory Space 0.
1: Performs Endian Transfer.
0: Does not perform Endian Transfer.
Please use the default state.
Base Address (Default: 0x0_0000_00)
Sets the G-Bus base bus address of Memory Space 0 for initiator access.
Can set the base address in 256-byte units.
10-59
Chapter 10 PCI Controller
38 37 36 35
EXFER
BSWAP
R/W R/W
0x0/0x1 0x1/0x0
7
Reserved
R
0x00
Description
0xD120
48
: Type
: Initial value
32
BA[35:32]
R/W : Type
0x0 : Initial value
16
: Type
: Initial value
0
: Type
: Initial value
Read/Write
⎯
R/W
R/W
R/W
R