Single Address Single Transfer From Memory To I/O (64-Bit Sram) - Toshiba TMPR4937 Manual

8.5.10

Single Address Single Transfer from Memory to I/O (64-bit SRAM)

SDCLK
CS*
ADDR [19:5]
RAS*
CAS*
WE*
CKE*
OE*
DQM [7:0]
ff
DATA [63:0]
ACK*
DMAREQ[n]
DMAACK[n]
DMADONE*
Figure 8.5.11 Single Address Single Transfer from Memory to I/O
0000
(Single Read of 64-bit Data from 64-bit SDRAM)
8-50
Chapter 8 DMA Controller
0040
00 ff