P2G I/O Space G-Bus Base Address Register (P2Giogbase) 0Xd198 - Toshiba TMPR4937 Manual

10.4.49 P2G I/O Space G-Bus Base Address Register (P2GIOGBASE)
63
47
Reserved
31
15
BA[15:8]
R/W
0x00
Bit Mnemonic Field Name
63:39 Reserved
38 P2GIOEN I/O Space Enable Target I/O Space Enable (Default: 0x0) Controls whether the I/O Space for
37 BSWAP Byte Swap
36 EXFER Endian Transfer
Memory Space
35:8 BA[35:8]
Base Address 2
7:1 Reserved
Figure 10.4.47 P2G I/O Space G-Bus Base Address Register
Reserved
39 38
P2GIOEN
R/W
0x0
BA[31:16]
R/W
0x0000
8 7
Description
target access is valid or invalid.
When this bit is set to invalid, Writes to the I/O Space Base Address
Register of the PCI Configuration Register become invalid. Also, "0" is
returned to Reads as a response.
1: Validates I/O Space for target access.
0: Invalidates I/O Space for target access.
Byte Swap Disable
(Default: Little Endian Mode: 0x1; Big Endian Mode: 0x0) Sets the byte
swapping of the I/O Space for target access.
1: Do not perform byte swapping.
0: Perform byte swapping.
Please use the default state in most situations. If this bit is changed to "1"
when in the Big Endian Mode, the byte order of transfer to the I/O Space
through DWORD (32-bit) access will not change.
Endian Transfer
(Default: Little Endian Mode: 0x0; Big Endian Mode: 0x1) Sets the Endian
Transfer of the I/O Space for target access.
1: Performs Endian Transfer.
0: Does not perform Endian Transfer.
Please use the default state.
Base Address 2 (Default: 0x000)
Sets the G-Bus base bus address of the I/O Space for target access. Can
set the base address in 256-byte units.
10-80
Chapter 10 PCI Controller
0xD198
37 36 35
EXFER BA[35:32]
BSWAP
R/W R/W R/W
0x0
0x0/0x1 0x1/0x0
Reserved
48
: Type
: Initial value
32
: Type
: Initial value
16
: Type
: Initial value
0
: Type
: Initial value
Read/Write
⎯
R/W
R/W
R/W
R/W
⎯