Toshiba TMPR4937 Manual page 159

DMAC0
DMA
Control 1
DM1MCR
Block
DM1MFDR
G-Bus
I/F
FIFO
(8 Double
Words)
DMA Channel Arbiter
Figure 8.2.2 DMA1 Controller Block Diagram
Chapter 8 DMA Controller
DM1CHAR0
DMA1
DREQ0
Channel 0 DM1SAR0
DM1DAR0
DACK0
DM1CNTR0
DM1SAIR0
DM1DAIR0
DM1CCR0
DM1CSR0
DM1CHAR1
DMA1
DREQ1
Channel 1 DM1SAR1
DM1DAR1
DMCK1
DM1CNTR1
DM1SAIR1
DM1DAIR1
DM1CCR1
DM1CSR1
DM1CHAR2
DMA1
DREQ2
Channel 2
DM1SAR2
DM1DAR2
DACK2
DM1CNTR2
DM1SAIR2
DM1DAIR2
DM1CCR2
DM1CSR2
DM1CHAR3
DMA1
DREQ3
Channel 3 DM1SAR3
DM1DAR3
DMCK3
DM1CNTR3
DM1SAIR3
DM1DAIR3
DM1CCR3
DM1CSR3
8-3
Internal I/O
(ACLC ch0)
Internal I/O
(ACLC ch1)
Internal I/O
(ACLC ch2)
Internal I/O
(ACLC ch3)