Pdmac Chain Address Register (Pdmca) 0Xd200 - Toshiba TMPR4937 Manual

10.4.58 PDMAC Chain Address Register (PDMCA)
63
47
31
15
Bits Mnemonic Field Name
63:36 Reserved
35:3 PDMCA Chain Address
2:0 Reserved
Reserved
Reserved
PDMCA[31:16]
R/W
Undefined
PDMCA[15:3]
R/W
Undefined
PDMAC Chain Address (Default is undefined)
The address of the next PDMAC Data Command Descriptor to be read is
specified by a G-Bus physical address on a 64-bit address boundary. This
register value is held without being affected by a Reset.
0 value judgement is performed when the lower 32 bits of this register are
rewritten. DMA transfer is automatically initiated if the result is not "0".
Figure 10.4.56 PDMAC Chain Address Register
10-89
Chapter 10 PCI Controller
0xD200
36 35
PDMCA[35:32]
3
Description
48
: Type
: Initial value
32
R/W : Type
undefined : Initial value
16
: Type
: Initial value
2 0
Reserved
: Type
: Initial value
Read/Write
⎯
R/W
⎯