0X8018 (Ch. 3) - Toshiba TMPR4937 Manual

9.4.1 SDRAM Channel Control Register (SDCCRn) 0x8000 (ch. 0)
When the SDCCRn is programmed using a sequence of 32-bit store instructions, the base address and
the address mask in the high-order 32-bit portion of the register must be written first, followed by the
Channel Enable bit in the low-order 32-bit portion.
63
47
31 29 28
ECC
R/W
0 0 0
15 14 13 12
RD MT ME
Reserved
R/W R/W R/W
1)
0 0 0
Bit Mnemonic Field Name
63:49 BA[35:21] Base Address
48 —
47:33 AM[35:21] Address Mask
32 —
31:29 ECC ECC/Parity Mode
28:16 —
BA
R/W
0x01FC/0x0000
AM
R/W
0x0000
11 10 9 8
SE CE BS
Reserved Reserved
R/W R/W R/W
1)
0 0 0
Base Address (Default: 0x01FC/0x0000)
Specifies the base address. The upper 15 bits [35:21] of the physical
address are compared to the value of this field.
(Note) Only the default for Channel 0 differs. Channel 0: 0x01FC, Others:
0x0000
— Reserved
Address Mask (Default: 0x0000)
Sets the valid bits for address comparison according to the base address.
0: Bits of the corresponding BA field are compared.
1: Bits of the corresponding BA field are not compared.
— Reserved
ECC/Parity mode (Default: 000)
Specifies the channel ECC/Parity type (refer to 9.3.10.1).
000: NOP Mode
001: EC Mode
010: ECC Mode
011: ECC + scrub Mode
100: Even Parity Mode
101: Odd Parity Mode
110: Reserved
110: Reserved
— Reserved
Figure 9.4.1 SDRAM Channel Control Register (1/2)
Chapter 9 SDRAM Controller
0x8008 (ch. 1)
0x8010 (ch. 2)

0x8018 (ch. 3)

Reserved
7 6 5 4
RS CS
R/W R/W
1)
000 000
Description
9-18
49 48
Reserved
:Type
:Initial value
33 32
Reserved
:Type
:Initial value
16
:Type
:Initial value
3 2 1 0
MW
Reserved
R/W :Type
1)
1 :Initial value
Read/Write
R/W
⎯
R/W
⎯
R/W
⎯