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Table 9.3.2 Address Signal Mapping (64-bit Data Bus) (2/2)
Row Address Width = 12
Column Address Width = 11
Address Bit
19
18
ADDR [19:5]
(B0)
(B1)
Column
26
27
Address
Row Address
26
27
Row Address Width = 13
Column Address Width = 8
Address Bit
19
18
ADDR [19:5]
(B0)
(B1)
Column
24
25
Address
Row Address
24
25
Row Address = 13
Column Address Width = 9
Address Bit
19
18
ADDR [19:5]
(B0)
(B1)
Column
25
26
Address
Row Address
25
26
Row Address Width = 13
Column Address Width = 10
Address Bit
19
18
ADDR [19:5]
(B0)
(B1)
Column
26
27
Address
Row Address
26
27
Row Address Width = 13
Column Address Width = 11
Address Bit
19
18
ADDR [19:5]
(B0)
(B1)
Column
27
28
Address
Row Address
27
28
Row Address Width = 13
Column Address Width = 12
Address Bit
19
18
ADDR [19:5]
(B0)
(B1)
Column
28
29
Address
Row Address
28
29
15
17
16
14
13
(AP)
26
25
L/H
24
23
26
22
21
20
19
15
17
16
14
13
(AP)
23
22
L/H
25
24
23
22
21
20
19
15
17
16
14
13
(AP)
23
22
L/H
25
24
23
22
21
20
19
15
17
16
14
13
(AP)
23
22
L/H
25
24
23
22
21
20
19
15
17
16
14
13
(AP)
23
26
L/H
25
24
23
22
21
20
19
15
17
16
14
13
(AP)
27
26
L/H
25
24
23
22
21
20
19
9-6
Chapter 9 SDRAM Controller
12
11
10
9
8
10
9
8
7
6
18
17
16
15
14
12
11
10
9
8
10
9
8
7
6
18
17
16
15
14
12
11
10
9
8
10
9
8
7
6
18
17
16
15
14
12
11
10
9
8
10
9
8
7
6
18
17
16
15
14
12
11
10
9
8
10
9
8
7
6
18
17
16
15
14
12
11
10
9
8
10
9
8
7
6
18
17
16
15
14
7
6
5
5
4
3
13
12
11
7
6
5
5
4
3
13
12
11
7
6
5
5
4
3
13
12
11
7
6
5
5
4
3
13
12
11
7
6
5
5
4
3
13
12
11
7
6
5
5
4
3
13
12
11
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