Dma Source Address Register (Dm0Sarn, Dm1Sarn) - Toshiba TMPR4937 Manual

8.4.4

DMA Source Address Register (DM0SARn, DM1SARn)

Offset Address: DMAC0 0xB008 (ch. 0) / 0xB048 (ch. 1) / 0xB088 (ch. 2) / 0xB0C8 (ch. 3)
63
47
31
15
Bits Mnemonic Field Name
⎯
63:36 Reserved
35:0 SADDR Source Address
DMAC1 0xB808 (ch. 0) / 0xB848 (ch. 1) / 0xB888 (ch. 2) / 0xB8C8 (ch. 3)
Reserved
Reserved
SADDR[31:16]
R/W
⎯
SADDR[15:0]
R/W
⎯
Source Address (Default: Undefined)
This field sets the physical address of the transfer source during Dual
Address transfer. This field sets the physical address of memory access
during Single Address transfer. This field is used for either Memory-to-I/O
or I/O-to-Memory transfers.
Refer to "8.3.7.1 Channel Register Settings During Single Address
Transfer" and "8.3.8.1 Channel Register Settings During Dual Address
Transfer" for more information.
During Burst transfer, the value changes once for each bus operation only
by the size that was transferred. During Single transfer, the value only
changes by the value specified by the DMA Source Address Increment
Register (DMSAIRn).
Figure 8.4.4 DMA Source Address Register
8-33
Chapter 8 DMA Controller
36 35
SADDR[35:32]
Description
48
: Type
: Initial value
32
: Type
R/W
⎯ : Initial value
16
: Type
: Initial value
0
: Type
: Initial value
Read/Write
⎯
R/W