Power Management Capability Register (Pmc) 0Xde - Toshiba TMPR4937 Manual

10.5.3 Power Management Capability Register (PMC)
15
PMESPT
R
0x19
Bit Mnemonic Field Name
PME Output
15:11 PMESPT
Support
10 D2SPT D2 Support
9 D1SPT D1 Support
8:6 Reserved
5 DSI DSI
4 Reserved
3 PMECLK PME Clock
Power
2:0 PMVER
Management I/F
Version
11 10 9 8
D2SPT D1SPT Reserved
R R
0 0
PME_ Support (Fixed Value: 0x09)
Indicates that the PME* signal can be output from the state where the bit is
set to "1".
Bit 15: Can output the PME* signal from the D3cold state.
Bit 14: Can output the PME* signal from the D3hot state.
Bit 13: Can output the PME* signal from the D2 state.
Bit 12: Can output the PME* signal from the D1 state.
Bit 11: Can output the PME* signal from the D0 state.
Note: With the TX4937 PCI Controller, it is possible to output the
PME* signal from the D0 and the D3hot states.
D2_Support (Fixed Value: 0)
0: Indicates that the D2 state is not supported.
D1_Support (Fixed Value: 0)
0: Indicates that the D1 state is not supported.
DSI (Fixed Value: 0)
0: Indicates that Device Specific Initialization is not required.
PME Clock (Fixed Value: 0)
0: Indicates that the PCI Clock is not required to assert the PME* signal.
Version (Fixed Value: 0x2)
2: Indicates compliance with "PCI Power Management Interface
Specification" Version 1.1.
Figure 10.5.3 PMC Register
10-101
Chapter 10 PCI Controller
0xDE
6 5 4 3
DSI
Reserved PMECLK
R R
0 0
Description
2 0
PMVER
R : Type
0x2 : Initial value
Read/Write
R
R
R
⎯
R
⎯
R
R