Toshiba TMPR4937 Manual page 459

Bits Mnemonic Field Name
Interrupt Source
17:16 IC16
Control 16
15:14 IC7 Interrupt Source
Control 7
13:12 IC6 Interrupt Source
Control 6
Interrupt Source
11:10 IC5
Control 5
9:8 IC4 Interrupt Source
Control 4
7:6 IC3 Interrupt Source
Control 3
5:4 IC2 Interrupt Source
Control 2
3:2 IC1 Interrupt Source
Control 1
1:0 IC0 Interrupt Source
Control 0
Interrupt Source Control 16 (Default: 00)
These bits specify the active state of PCIC interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 7 (Default: 00)
These bits specify the active state of external INT[5] interrupts.
00: Low level active
01: High level active
10: Falling edge active
11: Rising edge active
Interrupt Source Control 6 (Default: 00)
These bits specify the active state of external INT[4] interrupts.
00: Low level active
01: High level active
10: Falling edge active
11: Rising edge active
Interrupt Source Control 5 (Default: 00)
These bits specify the active state of external INT[3] interrupts.
00: Low level active
01: High level active
10: Falling edge active
11: Rising edge active
Interrupt Source Control 4 (Default: 00)
These bits specify the active state of external INT[2] interrupts.
00: Low level active
01: High level active
10: Falling edge active
11: Rising edge active
Interrupt Source Control 3 (Default: 00)
These bits specify the active state of external INT[1] interrupts.
00: Low level active
01: High level active
10: Falling edge active
11: Rising edge active
Interrupt Source Control 2 (Default: 00)
These bits specify the active state of external INT[0] interrupts.
00: Low level active
01: High level active
10: Falling edge active
11: Rising edge active
Interrupt Source Control 1 (Default: 00)
These bits specify the active state of TX49 Write Timeout Error interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 0 (Default: 00)
These bits specify the active state of ECC Error interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Figure 15.4.2 Interrupt Detection Mode Register 0 (2/2)
15-13
Chapter 15 Interrupt Controller
Explanation Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W