Toshiba TMPR4937 Manual page 399

12.4.6 Divide Register n (TMCCDRn)
31
15
Bits Mnemonic Field Name
31:3 Reserved
2:0 CCD Counter Clock
Divide Value
Reserved
Reserved
Description
Counter Clock Divide (Default: 000)
These bits specify the divide value when using the internal clock
(IMBUSCLK) as the counter input clock source. The binary value n is
n+1
divided by 2 .
1
000: Divide by 2 (f/2)
2
001: Divide by 2 (f/4)
3
010: Divide by 2 (f/8)
4
011: Divide by 2 (f/16)
5
100: Divide by 2 (f/32)
6
101: Divide by 2 (f/64)
7
110: Divide by 2 (f/128)
8
111: Divide by 2 (f/256)
Figure 12.4.6 Divide Register
12-15
Chapter 12 Timer/Counter
TMCCDR0 0xF020
TMCCDR1 0xF120
TMCCDR2 0xF220
3 2
CCD
R/W
000
16
: Type
: Initial value
0
: Type
: Initial value
Read/Write
⎯
R/W