Toshiba TMPR4937 Manual page 549

Page Rev 1.1 Manual
Table 8.3.3 Channel Register Setting Restrictions During
Dual Address Transfer
8-13 <DMSAIRn>
8/0/-8
8-13
Figure 9.4.4 ECC Control Register (1/2)
63
9-23
Figure 9.4.4 ECC Control Register (1/2)
55
9-23
Figure 9.4.4 ECC Control Register (1/2)
Modified the description of the DEEC (Diagnostic ECC)
field.
9-23
The value set by this field is output from CB[7:0] as the
check code when the ECCDM bit is set to "Enable."
Figure 9.4.5 ECC Status Register
15
9-25
— —
Figure 9.6.2 168-pin DIMM Connection Example
ADDR[16:5]
9-42
ADDR[18]
ADDR[17]
56
0x10
R
48
0x10
R
8
FRRS
R
— — — —
128MB un
A[11:0]
BA0
BA1
DQMB[7:0]
5
TMPR4937 Revision History
Changes and Additions to Rev 1.1
8/0/-8
Table 8.3.3 Channel Register Setting Restrictions During
Dual Address Transfer
Added the following note.
: When DMSAIRn is set to 0, read access from source
device is performed only one time per transmission
specified by DMCCRn.XFSZ. For this reason, transfer
can not be performed burst transfer to the I/O device
which performs FIFO operation.
63
MDLNO
0x10
55
VERNO
0x10
The value set by this field is output from CB[7:0] as the
check code when the DM bit is set to "Enable."
15
ERRS
R
— — —
ADDR[16:5]
A[11:0]
ADDR[19]
BA0
ADDR[18]
BA1
DQMB[7:0]
56
48
8
— — —
128MB un