Toshiba TMPR4937 Manual page 310

10.4.25 PCI Bus Arbiter Status Register (PBASTATUS)
This register is only valid when using the on-chip PCI Bus Arbiter.
31
15
Bit Mnemonic Field Name
31:1 Reserved
0 BM Broken Master
Detected
Reserved
Reserved
Broken Master Detected (Default: 0)
This bit indicates that a Broken Master was detected. This bit is set to "1" if
even one of the bits in the PCI Bus Arbiter Broken Master Register
(PBABM) is "1".
1: Indicates that a Broken Master was detected.
0: Indicates that no Broken Master has been detected.
Figure 10.4.23 PCI Bus Arbiter Status Register
10-52
Chapter 10 PCI Controller
0xD108
Description
16
: Type
: Initial value
1 0
BM
R/W1C : Type
0 : Initial value
Read/Write
⎯
R/W1C