Toshiba TMPR4937 Manual page 240

Bit Mnemonic Field Name
Single-Bit Error
8 SEI
Interrupt Enable
7:1 — —
0 ECCE ECC Enable
Single-Bit Error Interrupt Enable (Default: 0)
Specifies whether to generate an interrupt during a single-bit error.
0: Disable
1: Enable
Reserved
ECC Enable (Default: 0)
Specifies whether to enable the ECC/Parity function. When disabled, the
ECC function will not operate even if the ECC Parity Mode field
(SDCCRn.ECC) selects the ECC/Parity Mode.
0: Disable
1: Enable
Figure 9.4.4 ECC Control Register (2/2)
9-24
Chapter 9 SDRAM Controller
Description Read/Write
R/W
⎯
R/W