Toshiba TMPR4937 Manual page 172

Source Address
63 0
a0
a8
b0
b8
c0
c8
d0
d8
e0
e8
f0
f8
00
08
10
18
20
28
30
38
(a) Address offset is equivalent
63 0
a0
a8
b0
b8
c0
c8
d0
d8
e0
e8
f0
f8
00
08
10
18
20
28
30
38
40
48
50
58
60
(b) Address offset differs
Figure 8.3.4 Dual Address Burst Transfer (DMCCRn.USEXFSZ = 0)
Chapter 8 DMA Controller
FIFO (8 Double Words)
8-16
Destination Address
63 0
20
28
30
38
40
48
50
58
60
68
70
78
80
88
90
98
a0
a8
b0
b8
63 0
20
28
30
38
40
48
50
58
60
68
70
78
80
88
90
98
a0
a8
b0
b8
c0
c8
d0
d8
e0