Fifo Control Register 0 (Sifcr0) 0Xf310 (Ch. 0) Fifo Control Register 1 (Sifcr1) 0Xf410 (Ch. 1) - Toshiba TMPR4937 Manual

11.4.5 FIFO Control Register 0 (SIFCR0)
FIFO Control Register 1 (SIFCR1)
These registers set control of the Transmit/Receive FIFO buffer.
31
15 14
Reserved
SWRST
R/W
0
Bit Mnemonic Field Name
⎯
31:16 Reserved
15 SWRST Software Reset
⎯
14:9 Reserved
Receive FIFO
8:7 RDIL
Request Trigger
Level
⎯
6:5 Reserved
4:3 TDIL Transmit FIFO
Request Trigger
Level
2 TFRST Transmit FIFO
Reset
1 RFRST Receive FIFO
Reset
0 FRSTE FIFO Reset
Enable
0xF310 (Ch. 0)
0xF410 (Ch. 1)
Reserved
9 8 7 6
RDIL Reserved
R/W
00
Description
Software Reset (Default: 0)
This field performs SIO resets except for the FIFOs. Setting this bit to "1"
initiates the reset. Set registers are also initialized. This bit returns to "0"
when initialization is complete.
0: Normal operation
1: SIO software reset
Receive FIFO DMA/Interrupt Trigger Level (Default: 00)
This register sets the level for reception data transfer from the Receive
FIFO.
00: 1 Byte
01: 4 Bytes
10: 8 Bytes
11: 12 Bytes
Transmit FIFO DMA/Interrupt Trigger Level (Default: 00)
This register sets the level for transmission data transfer to the Transmit
FIFO.
00: 1 Byte
01: 4 Bytes
10: 8 Bytes
11: Setting disabled
Transmit FIFO Reset (Default: 0)
The Transmit FIFO buffer is reset when this bit is set. This bit is valid when
the FIFO Reset Enable bit (FRSTE) is set. Cancel reset by using the
software to clear this bit.
0: During operation
1: Reset Transmit FIFO
Receive FIFO Reset (Default: 0)
The Receive FIFO buffer is reset when this bit is set. This bit is valid when
the FIFO Reset Enable bit (FRSTE) is set. Cancel reset by using the
software to clear this bit.
0: During operation
1: Reset Receive FIFO
FIFO Reset Enable (Default: 0)
This field is the Reset Enable for the Transmit/Receive FIFO buffer. The
FIFO is reset by combining the Transmit FIFO Reset bit (TFRST) and
Receive FIFO Reset bit (RFRST).
0: During operation
1: Reset Enable
Figure 11.4.5 FIFO Control Register
11-20
Chapter 11 Serial I/O Port
5 4 3 2
TDIL
TFRST RFRST FRSTE
R/W R/W
00 0
⎯
⎯
⎯
16
: Type
: Initial value
1 0
R/W R/W : Type
0 0 : Initial value
Read/Write
⎯
R/W
⎯
R/W
⎯
R/W
R/W
R/W
R/W