Toshiba TMPR4937 Manual page 97

Clock Input/Output
PCICLK[5:0] Output Clock supplied to devices on the PCI bus.
The PCICLKEN bit of the PCFG register can
disable the output of PCICLK.
The frequency depends on boot configuration
signals ADDR[11:10] or the PCIDIVMODE field of
the CCFG register.
Initial Value of PCIDIVMODE[0] is 0.
CCFG_PCIDIVMODE[2:0]
Note: PCICLK[5:0] can supply clock pulses at 66
PCI bus clock. The built-in PCI controller of the
PCICLKIN Input
TX4937 operates with this clock.
Note: To achieve an accurate phase match with
PCICLKO Internal signal Clock supplied to the PCI controller. PCICLKO is
generated by PLL2 based on PCICLKIN.
PCICLKO has the same frequency and phase as
those of PCICLKIN (input pin).
EEPROM_SK Output Clock for serial EEPROM used to initially set the
PIC configuration.
SCLK Input Input clock for SIO. SCLK is shared by SIO0 and
SIO1.
TCLK Input Input clock for timers. TCLK is shared by TMR0,
TMR1, and TMR2.
BITCLK Input Input clock for the AC-link controller.
The pin is shared with the PIO[2] signal.
TCK Input Input clock for JTAG.
DCLK Output Clock output for the real-time debugging system.
Table 6.1.1 TX4937 Clock Signals (2/2)
Description
=001: CPUCLK divided by 4
=011: CPUCLK divided by 4.5
=101: CPUCLK divided by 5
=111: CPUCLK divided by 5.5
=000: CPUCLK divided by 8
=010: CPUCLK divided by 9
=100: CPUCLK divided by 10
=110: CPUCLK divided by 11
or 33 MHz when the CPUCLK frequency is
set to 300.
The setting is: 011, 010
the external clock, PCICLK[5:0] or the PCI
clock output from another PCI device must
be supplied to PCICLKIN.
Chapter 6 Clocks
Related
Configuration Signals
(Refer to Section
3.2.)
ADDR[11:10]
⎯
⎯
⎯
⎯
⎯
ADDR[9]
⎯
⎯
6-3
Related Registers
(Refer to Chapters 5
and 10.)
CCFG.PCIDIVMODE
PCFG.PCICLKEN[5:0]
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯