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Rev 1.1 Manual
Modified line 8 of Section 20.3, Initializing the Extended
EJTAG Interface
The above methods must be performed while the
20-7
MASTERCLK signal is being input. Also, externally fix
the TRST* signal to GND when not using an emulation
probe. The G-Bus Time Out Detection function is disabled
when the TRST* signal is deasserted. (Refer to Section
5.1.1.)
Figure 21.5.1 Timing Diagram: MASTERCLK
0.8 V
21-5
MASTERCL
0.2 V
Figure 21.5.2 Timing Diagram: Power On Reset
VddIN, VddIO
PLL_Vdd1_A,
PLL_Vdd2_A
MASTERCLK
21-5
CGRESET*
RESET*
Figure 22.1.1 Pinout Diagram (1/2)
DMAACK
DMAACK
7
[2]
[3]
22-2
6
CE[4]*
CE[3]*
5
CE[5]*
VddIO
Table 22.1.1 Pin Cross Reference by Pin Number (1/2)
Modified the pin name of the E6 pin.
22-4
SD[1]
Table 22.1.2 Pin Cross Reference by Pin Name (2/2)
Modified the pin name of the E6 pin.
22-7
SD[1]
t
MCP
CC
CC
MASTERCLK Oscillation Stabilit
t
MCP_PLL
CE[1]*
CE[0]*
VddIO
TOP
CE[2]*
VSS
SD[1]
BYPASSP
ACE*
VSS
VddIN
LL*
7
TMPR4937 Revision History
Changes and Additions to Rev 1.1
The above methods must be performed while the
MASTERCLK signal is being input.
The G-Bus Time Out Detection function is disabled when
the TRST* signal is deasserted. (Refer to Section 5.1.1.)
0.8 V
CC
MASTERCLK
0.2 V
CC
Changed a signal name in the figure and added a note.
* 1)
V
, V
CCInt
CCIO
PLL_Vdd1_A,
MASTERCLK Oscillation Stabilit
PLL_Vdd2_A
MASTERCLK
CGRESET*
RESET*
* 1)
V
and V
must start up simultaneously, or
CCInt
CCIO
V
must be first.
CCInt
The difference of the stand up time of a power supply
within in 100 m seconds.
DMAACK
DMAACK
7
CE[1]*
[2]
[3]
6
CE[4]*
CE[3]*
CE[2]*
5
CE[5]*
VddIO
ACE*
SDIN[1]
SDIN[1]
t
MCP
t
MCP_PLL
CE[0]*
VddIO
TOP
VSS
SDIN[1]
BYPASSP
VSS
VddIN
LL*
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