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3.1.3
External Interface Signals
Signal Name
Type
SYSCLK
Output
System Clock
Clock for external I/O devices.
Outputs a clock in full speed mode (at the same frequency as the G-Bus clock
(GBUSCLK) frequency), half speed mode (at one half the GBUSCLK frequency), third
speed mode (at one third the GBUSCLK frequency), or quarter speed mode (at one
quarter the GBUSCLK frequency). The boot configuration signals on the ADDR[14:13]
pins select which speed mode will be used.
When this clock signal is not used, the pin can be set to H using the SYSCLK Enable
bit of the configuration register (CCFG.SYSCLKEN).
ACE*
Output
Address Clock Enable
Latch enable signal for the high-order address bits of ADDR.
CE[7:0]*
Output
Chip Enable
Chip select signals for ROM, SRAM, and I/O devices (refer to Section "3.3 Pin
multiplex").
OE*
Output
Output Enable
Output enable signal for ROM, SRAM, and I/O devices.
SWE*
Output
Write Enable
Write enable signal for SRAM and I/O devices.
BWE[3:0]*
Output
Byte Enable/Byte Write Enable
/BE[3:0]*
BE[3:0]* indicate a valid data position on the data bus DATA[31:0] during read and
write bus operation. In 16-bit bus mode, only BE[1:0]* are used. In 8-bit bus mode,
only BE[0]* is used.
BWE[3:0]* indicate a valid data position on the data bus DATA[31:0] during write bus
operation. In 16-bit bus mode, only BWE[1:0]* are used. In 8-bit bus mode, only
BWE[0]* is used.
The following shows the correspondence between BE[3:0]*/BWE[3:0]* and the data
bus signals.
BE[3]*/BWE[3]*:
BE[2]*/BWE[2]*:
BE[1]*/BWE[1]*:
BE[0]*/BWE[0]*:
The boot configuration signal on the DATA[5] pin and the EBCCRn.BC bit of the
external bus controller determine whether the signals are used as BE[3:0]* or
BWE[3:0]*.
ACK*/ READY Input/output
Data Acknowledge/Ready
PU
Flow control signal (refer to Section "7.3.6 Access Modes").
Table 3.1.3 External Interface Signals
Description
DATA[31:24]
DATA[23:16]
DATA[15:8]
DATA[7:0]
3-3
Chapter 3 Signals
Initial State
High
High
All High
High
High
All High
High
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