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Rev 1.1 Manual
Figure 5.2.6 G-Bus Arbiter Control Register
15
Reserved
5-13
7
6
Reserved
Figure 6.3.1 Power-On Sequence
At least 100 ms (T.B.D)
PLL settling time (T.B.D)
6-6
ed back)
7-11
Figure 7.3.3 Ready Mode
7-11
10
9
⎯
ARBMD
R/W
R/W
1
5
PRIORITY
R/W
00_01_10
(T.B.D)
PLL settling time (T.B.D)
EBCCRn.PWT:WT=2
Start Ready Check
3
TMPR4937 Revision History
Changes and Additions to Rev 1.1
8
15
14
Reserved
1
000_001_010_011_100
0
000_001_010_011_100
PLL settling time
ed back)
Added the following text to line 8 to Section 7.3.6.3, Ready
Mode
When the number of wait cycles is 0, READY check is
started in 1 cycle after asserting the CE* signal. When the
number of wait cycles is other than zero, after waiting only
for the specified number of cycles, READY check is started.
EBCCRn.PWT:WT=2
Start Ready Check
PRIORITY
R/W
0
PRIORITY
R/W
PLL settling time
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