Ecc Status Register (Eccsr) 0Xa008 - Toshiba TMPR4937 Manual

9.4.5 ECC Status Register (ECCSR)
63
— — — —
47
— — — —
31 28
ERRAD
Reserved
R
— — — —
15
ERRS
R
— — — —
Bit Mnemonic Field Name
63:28 ERRAD Error Address
27 — —
26:24 ERRMODE Error ECC/Parity
Mode
23:22 — —
21 ERRMW Error Memory
Width
20:16 — —
15:8 ERRS Error Syndrome
7:2 — —
1 MBERR Multi-Bit Error
0 SBERR Single-Bit Error
ERRAD
R
— — — —
ERRAD
R
— — — —
27 26 24
ERRMODE
R
— — —
8
— — — —
Error Address (Default: Unknown)
A 36-bit physical address is set when an error occurs. This address is
retained until either SBERR or MBERR is cleared. This field is Read Only.
Reserved
Error ECC Mode (Default: Unknown)
The ECC/Parity Mode is set when an error occurs. This address is retained
until either SBERR or MBERR is cleared. This field is Read Only.
Reserved
Error Memory Width (Default: Unknown)
The memory data width is set when an error occurs. This address is
retained until either SBERR or MBERR is cleared. This field is Read Only.
0: 64 bits
1: 32 bits
Reserved
Error Syndrome (Default: Unknown)
The error syndrome for when errors occur is set. The syndrome is retained
until either SBERR or MBERR is cleared. This field is Read Only.
Reserved
Multi-Bit Error (Default: 0)
This bit is set to "1" when a multi-bit error occurs, or when a parity error
occurs while in the Parity Mode. Once a multi-bit error occurs, until this bit
is cleared, no status in the Status Register is updated even if new multi-
/single-bit errors occur.
0: No error
1: Generate error
Single-Bit Error (Default: 0)
This bit is set to "1" when a single-bit error occurs. Once a single-bit error
occurs, until this bit is cleared, no status in the Status Register is updated
even if new single-bit error occurs. If a multi-bit error occurs, status is
updated regardless of whether a single-bit error has occurred or not.
0: No error
1: Generate error
Figure 9.4.5 ECC Status Register
9-25
Chapter 9 SDRAM Controller
0xA008
— — — —
— — — —
23 22 21 20
Reserved
ERRMW
R
— — —
7
Reserved
Description
48
:Type
— — — — :Initial value
32
:Type
— — — — :Initial value
16
Reserved
:Type
:Initial value
2 1 0
MBERR SBERR
R/W R/W :Type
0 0 :Initial value
Read/Write
R
⎯
R
⎯
R
⎯
R
⎯
R/W
R/W