Table of Contents
Advertisement
"A"
+08
+10
+18
+20
+28
+30
+38
"B"
+08
+10
+18
+20
+28
+30
+38
"C"
+08
+10
+18
+20
+28
+30
+38
Figure 8.3.5 DMA Command Descriptor Chain
The sequence of Chain DMA transfer is as follows below.
1.
Select DMA request signal
When performing external I/O or internal I/O DMA, set the DMA Request Select field
(PCFG.DMASEL) of the Pin Configuration Register.
2.
Set the Master Enable bit
Set the Master Enable bit (DMMCR.MSTEN) of the DMA Master Control Register.
3.
Structure of the DMA command Descriptor chain
Construct the DMA Command Descriptor Chain in memory.
4.
Set the Count Register
Set "0" to the DMA Count Register (DMCNTRn) .
Sets the DMA Source Address Increment Register (DMSAIRn) and DMA destination Address
Increment Register (MMDAIRn).
5.
Clear the DMA Channel Status Register (DMCSRn)
Clear the status of the previous DMA transfer.
6.
Set the DMA Channel Control Register (DMCCRn).
Chapter 8 DMA Controller
"D"
+08
+10
+18
+20
+28
+30
+38
"E"
+08
+10
+18
+20
+28
+30
+38
8-19
Advertisement
Table of Contents
